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drm/amdgpu: update nbio v7_4 ip header files
Add mmBIF_INTR_CNTL and its shift mask. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 5 additions and 5 deletions
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@ -2793,8 +2793,8 @@
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#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2
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#define mmBIF_FB_EN 0x00ff
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#define mmBIF_FB_EN_BASE_IDX 2
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#define mmBIF_BUSY_DELAY_CNTR 0x0100
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#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2
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#define mmBIF_INTR_CNTL 0x0100
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#define mmBIF_INTR_CNTL_BASE_IDX 2
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#define mmBIF_MST_TRANS_PENDING_VF 0x0109
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#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2
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#define mmBIF_SLV_TRANS_PENDING_VF 0x010a
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@ -20420,9 +20420,9 @@
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#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
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#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
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#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
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//BIF_BUSY_DELAY_CNTR
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#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
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#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
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//BIF_INTR_CNTL
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#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
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#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
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//BIF_MST_TRANS_PENDING_VF
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#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
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#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
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