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drm/amdgpu: implement UVD6 check/pre/post_soft_reset
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1015a1b175
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3 changed files with 70 additions and 5 deletions
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@ -1689,6 +1689,7 @@ struct amdgpu_uvd {
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bool address_64_bit;
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bool use_ctx_buf;
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struct amd_sched_entity entity;
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uint32_t srbm_soft_reset;
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};
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/*
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@ -1977,7 +1977,6 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
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{
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if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) {
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@ -754,14 +754,76 @@ static int uvd_v6_0_wait_for_idle(void *handle)
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return -ETIMEDOUT;
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}
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static int uvd_v6_0_soft_reset(void *handle)
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#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
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static int uvd_v6_0_check_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 srbm_soft_reset = 0;
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u32 tmp = RREG32(mmSRBM_STATUS);
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if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
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REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
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(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
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srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
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if (srbm_soft_reset) {
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = true;
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adev->uvd.srbm_soft_reset = srbm_soft_reset;
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} else {
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = false;
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adev->uvd.srbm_soft_reset = 0;
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}
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return 0;
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}
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static int uvd_v6_0_pre_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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uvd_v6_0_stop(adev);
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
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return 0;
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uvd_v6_0_stop(adev);
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return 0;
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}
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static int uvd_v6_0_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 srbm_soft_reset;
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
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return 0;
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srbm_soft_reset = adev->uvd.srbm_soft_reset;
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if (srbm_soft_reset) {
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u32 tmp;
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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}
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return 0;
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}
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static int uvd_v6_0_post_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
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return 0;
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WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
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~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
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mdelay(5);
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return uvd_v6_0_start(adev);
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@ -966,7 +1028,10 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
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.resume = uvd_v6_0_resume,
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.is_idle = uvd_v6_0_is_idle,
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.wait_for_idle = uvd_v6_0_wait_for_idle,
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.check_soft_reset = uvd_v6_0_check_soft_reset,
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.pre_soft_reset = uvd_v6_0_pre_soft_reset,
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.soft_reset = uvd_v6_0_soft_reset,
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.post_soft_reset = uvd_v6_0_post_soft_reset,
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.set_clockgating_state = uvd_v6_0_set_clockgating_state,
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.set_powergating_state = uvd_v6_0_set_powergating_state,
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};
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