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dt-bindings: Update headers for Tegra234
Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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2 changed files with 24 additions and 5 deletions
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@ -4,11 +4,22 @@
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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/**
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* @file
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/** @brief output of gate CLK_ENB_FUSE */
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123
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#define TEGRA234_CLK_SDMMC4 123U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155
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#define TEGRA234_CLK_UARTA 155U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
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#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief 32K input clock provided by PMIC */
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#define TEGRA234_CLK_CLK_32K 289U
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#endif
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#endif
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define TEGRA234_RESET_SDMMC4 85
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/**
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#define TEGRA234_RESET_UARTA 100
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* @file
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* @defgroup bpmp_reset_ids Reset ID's
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA234_RESET_SDMMC4 85U
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#define TEGRA234_RESET_UARTA 100U
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/** @} */
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#endif
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#endif
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