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arm64: dts: lg: Fix SP805 clocks

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The SP805 DT binding requires two clocks to be specified, but the two
LG platform DTs currently only specify one clock.

In practice, Linux would pick a clock named "apb_pclk" for the bus
clock, and the Linux (and U-Boot) SP805 driver would use the first clock
to derive the actual watchdog counter frequency.

Since currently both are the very same clock, we can just double the
clock reference, and add the correct clock-names, to match the binding.

Link: https://lore.kernel.org/r/20200907121831.242281-6-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Andre Przywara 2020-09-07 13:18:30 +01:00 committed by Olof Johansson
parent f6320e326f
commit fc772314a3
2 changed files with 4 additions and 4 deletions
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4
arch/arm64/boot/dts/lg/lg1312.dtsi
View file

@ -141,8 +141,8 @@ wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xfd200000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "wdog_clk", "apb_pclk";
};
uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";

4
arch/arm64/boot/dts/lg/lg1313.dtsi
View file

@ -141,8 +141,8 @@ wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xfd200000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "wdog_clk", "apb_pclk";
};
uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";