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sata_mv: simplify request/response queue handling
Try and simplify handling of the request/response queues. Maintain the cached copies of queue indexes in a fully-masked state, rather than having each use of them have to do the masking. Split off handling of a single crpb response into a separate function, to reduce complexity in the main mv_process_crpb_entries() routine. Ignore the rarely-valid error bits from the crpb status field, as we already handle that information in mv_err_intr(). For now, preserve the rest of the original logic. A later patch will deal with fixing that separately. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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1cfd19aeb8
commit
fcfb1f77ce
1 changed files with 56 additions and 53 deletions
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@ -804,7 +804,8 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
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/*
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* initialize request queue
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*/
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index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
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pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
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index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
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WARN_ON(pp->crqb_dma & 0x3ff);
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writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
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@ -820,7 +821,8 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
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/*
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* initialize response queue
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*/
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index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT;
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pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
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index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
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WARN_ON(pp->crpb_dma & 0xff);
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writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
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@ -1312,7 +1314,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
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flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
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/* get current queue index from software */
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in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
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in_index = pp->req_idx;
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pp->crqb[in_index].sg_addr =
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cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
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@ -1404,7 +1406,7 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
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flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
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/* get current queue index from software */
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in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
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in_index = pp->req_idx;
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crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
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crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
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@ -1471,9 +1473,8 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
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mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
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pp->req_idx++;
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in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
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pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
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in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
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/* and write the request in pointer to kick the EDMA to life */
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writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
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@ -1607,70 +1608,72 @@ static void mv_intr_pio(struct ata_port *ap)
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ata_qc_complete(qc);
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}
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static void mv_intr_edma(struct ata_port *ap)
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static void mv_process_crpb_response(struct ata_port *ap,
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struct mv_crpb *response, unsigned int tag, int ncq_enabled)
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{
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
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if (qc) {
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u8 ata_status;
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u16 edma_status = le16_to_cpu(response->flags);
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/*
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* edma_status from a response queue entry:
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* LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
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* MSB is saved ATA status from command completion.
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*/
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if (!ncq_enabled) {
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u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
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if (err_cause) {
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/*
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* Error will be seen/handled by mv_err_intr().
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* So do nothing at all here.
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*/
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return;
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}
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}
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ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
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qc->err_mask |= ac_err_mask(ata_status);
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ata_qc_complete(qc);
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} else {
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ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
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__func__, tag);
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}
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}
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static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
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{
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void __iomem *port_mmio = mv_ap_base(ap);
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_port_priv *pp = ap->private_data;
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struct ata_queued_cmd *qc;
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u32 out_index, in_index;
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u32 in_index;
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bool work_done = false;
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int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
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/* get h/w response queue pointer */
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/* Get the hardware queue position index */
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in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
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>> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
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while (1) {
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u16 status;
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/* Process new responses from since the last time we looked */
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while (in_index != pp->resp_idx) {
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unsigned int tag;
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struct mv_crpb *response = &pp->crpb[pp->resp_idx];
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/* get s/w response queue last-read pointer, and compare */
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out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK;
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if (in_index == out_index)
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break;
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pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
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/* 50xx: get active ATA command */
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if (IS_GEN_I(hpriv))
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if (IS_GEN_I(hpriv)) {
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/* 50xx: no NCQ, only one command active at a time */
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tag = ap->link.active_tag;
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/* Gen II/IIE: get active ATA command via tag, to enable
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* support for queueing. this works transparently for
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* queued and non-queued modes.
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*/
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else
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tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f;
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qc = ata_qc_from_tag(ap, tag);
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/* For non-NCQ mode, the lower 8 bits of status
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* are from EDMA_ERR_IRQ_CAUSE_OFS,
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* which should be zero if all went well.
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*/
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status = le16_to_cpu(pp->crpb[out_index].flags);
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if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
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mv_err_intr(ap, qc);
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return;
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} else {
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/* Gen II/IIE: get command tag from CRPB entry */
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tag = le16_to_cpu(response->id) & 0x1f;
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}
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/* and finally, complete the ATA command */
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if (qc) {
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qc->err_mask |=
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ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT);
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ata_qc_complete(qc);
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}
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/* advance software response queue pointer, to
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* indicate (after the loop completes) to hardware
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* that we have consumed a response queue entry.
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*/
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mv_process_crpb_response(ap, response, tag, ncq_enabled);
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work_done = true;
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pp->resp_idx++;
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}
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/* Update the software queue position index in hardware */
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if (work_done)
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writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
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(out_index << EDMA_RSP_Q_PTR_SHIFT),
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(pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
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port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
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}
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@ -1748,7 +1751,7 @@ static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
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if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
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if ((DMA_IRQ << hardport) & hc_irq_cause)
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mv_intr_edma(ap);
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mv_process_crpb_entries(ap, pp);
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} else {
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if ((DEV_IRQ << hardport) & hc_irq_cause)
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mv_intr_pio(ap);
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