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drm: rcar-du: Fix H/V sync signal polarity configuration
The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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1 changed files with 2 additions and 2 deletions
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@ -149,8 +149,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
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/* Signal polarities */
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value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
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| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
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value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
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| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
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| DSMR_DIPM_DISP | DSMR_CSPM;
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rcar_du_crtc_write(rcrtc, DSMR, value);
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