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[ARM] 2883/1: PXA Sharpsl: Add detection of new PXA based Zaurii machine types
Patch from Richard Purdie Add machine detection routines for several new models of PXA based Zaurii (SL-C3000 - Spitz, SL-C1000 - Akita, SL-C3100 - Borzoi, SL-C6000 - Tosa). Sharp continue to use broken bootloaders in ROM. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Richard Purdie
Russell King
parent
7dfe508a82
commit
fd6480f27e
1 changed files with 86 additions and 27 deletions
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@ -7,7 +7,8 @@
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* so we have to figure out the machine for ourselves...
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*
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* Support for Poodle, Corgi (SL-C700), Shepherd (SL-C750)
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* and Husky (SL-C760).
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* Husky (SL-C760), Tosa (SL-C6000), Spitz (SL-C3000),
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* Akita (SL-C1000) and Borzoi (SL-C3100).
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*
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*/
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@ -23,6 +24,22 @@
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__SharpSL_start:
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/* Check for TC6393 - if found we have a Tosa */
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ldr r7, .TOSAID
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mov r1, #0x10000000 @ Base address of TC6393 chip
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mov r6, #0x03
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ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
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cmp r6, r3
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beq .SHARPEND @ Success -> tosa
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/* Check for pxa270 - if found, branch */
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mrc p15, 0, r4, c0, c0 @ Get Processor ID
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and r4, r4, #0xffffff00
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ldr r3, .PXA270ID
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cmp r4, r3
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beq .PXA270
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/* Check for w100 - if not found we have a Poodle */
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ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
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mov r6, #0x31 @ Load Magic Init value
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@ -30,7 +47,7 @@ __SharpSL_start:
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mov r5, #0x3000
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.W100LOOP:
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subs r5, r5, #1
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bne .W100LOOP
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bne .W100LOOP
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mov r6, #0x30 @ Load 2nd Magic Init value
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str r6, [r1, #0x280] @ to SCRATCH_UMSK
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@ -40,45 +57,52 @@ __SharpSL_start:
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cmp r6, r3
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bne .SHARPEND @ We have no w100 - Poodle
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mrc p15, 0, r6, c0, c0 @ Get Processor ID
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and r6, r6, #0xffffff00
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/* Check for pxa250 - if found we have a Corgi */
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ldr r7, .CORGIID
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ldr r3, .PXA255ID
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cmp r6, r3
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cmp r4, r3
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blo .SHARPEND @ We have a PXA250 - Corgi
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mov r1, #0x0c000000 @ Base address of NAND chip
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ldrb r3, [r1, #24] @ Load FLASHCTL
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bic r3, r3, #0x11 @ SET NCE
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orr r3, r3, #0x0a @ SET CLR + FLWP
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strb r3, [r1, #24] @ Save to FLASHCTL
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mov r2, #0x90 @ Command "readid"
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strb r2, [r1, #20] @ Save to FLASHIO
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bic r3, r3, #2 @ CLR CLE
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orr r3, r3, #4 @ SET ALE
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strb r3, [r1, #24] @ Save to FLASHCTL
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mov r2, #0 @ Address 0x00
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strb r2, [r1, #20] @ Save to FLASHIO
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bic r3, r3, #4 @ CLR ALE
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strb r3, [r1, #24] @ Save to FLASHCTL
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.SHARP1:
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ldrb r3, [r1, #24] @ Load FLASHCTL
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tst r3, #32 @ Is chip ready?
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beq .SHARP1
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ldrb r2, [r1, #20] @ NAND Manufacturer ID
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ldrb r3, [r1, #20] @ NAND Chip ID
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/* Check for 64MiB flash - if found we have a Shepherd */
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bl get_flash_ids
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ldr r7, .SHEPHERDID
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cmp r3, #0x76 @ 64MiB flash
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beq .SHARPEND @ We have Shepherd
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/* Must be a Husky */
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ldr r7, .HUSKYID @ Must be Husky
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b .SHARPEND
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.PXA270:
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/* Check for 16MiB flash - if found we have Spitz */
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bl get_flash_ids
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ldr r7, .SPITZID
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cmp r3, #0x73 @ 16MiB flash
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beq .SHARPEND @ We have Spitz
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/* Check for a second SCOOP chip - if found we have Borzoi */
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ldr r1, .SCOOP2ADDR
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ldr r7, .BORZOIID
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mov r6, #0x0140
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strh r6, [r1]
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ldrh r6, [r1]
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cmp r6, #0x0140
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beq .SHARPEND @ We have Borzoi
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/* Must be Akita */
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ldr r7, .AKITAID
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b .SHARPEND @ We have Borzoi
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.PXA255ID:
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.word 0x69052d00 @ PXA255 Processor ID
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.PXA270ID:
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.word 0x69054100 @ PXA270 Processor ID
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.W100ID:
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.word 0x57411002 @ w100 Chip ID
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.W100ADDR:
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.word 0x08010000 @ w100 Chip ID Reg Address
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.SCOOP2ADDR:
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.word 0x08800040
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.POODLEID:
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.word MACH_TYPE_POODLE
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.CORGIID:
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@ -87,6 +111,41 @@ __SharpSL_start:
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.word MACH_TYPE_SHEPHERD
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.HUSKYID:
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.word MACH_TYPE_HUSKY
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.TOSAID:
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.word MACH_TYPE_TOSA
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.SPITZID:
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.word MACH_TYPE_SPITZ
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.AKITAID:
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.word MACH_TYPE_AKITA
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.BORZOIID:
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.word MACH_TYPE_BORZOI
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/*
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* Return: r2 - NAND Manufacturer ID
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* r3 - NAND Chip ID
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* Corrupts: r1
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*/
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get_flash_ids:
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mov r1, #0x0c000000 @ Base address of NAND chip
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ldrb r3, [r1, #24] @ Load FLASHCTL
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bic r3, r3, #0x11 @ SET NCE
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orr r3, r3, #0x0a @ SET CLR + FLWP
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strb r3, [r1, #24] @ Save to FLASHCTL
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mov r2, #0x90 @ Command "readid"
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strb r2, [r1, #20] @ Save to FLASHIO
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bic r3, r3, #2 @ CLR CLE
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orr r3, r3, #4 @ SET ALE
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strb r3, [r1, #24] @ Save to FLASHCTL
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mov r2, #0 @ Address 0x00
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strb r2, [r1, #20] @ Save to FLASHIO
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bic r3, r3, #4 @ CLR ALE
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strb r3, [r1, #24] @ Save to FLASHCTL
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.fids1:
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ldrb r3, [r1, #24] @ Load FLASHCTL
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tst r3, #32 @ Is chip ready?
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beq .fids1
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ldrb r2, [r1, #20] @ NAND Manufacturer ID
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ldrb r3, [r1, #20] @ NAND Chip ID
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mov pc, lr
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.SHARPEND:
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