mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
drm/i915/gt: Call intel_gt_sanitize() directly
Assume all responsibility for operating on the HW to sanitize the GT
state upon load/resume in intel_gt_sanitize() itself.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191101141009.15581-1-chris@chris-wilson.co.uk
(cherry picked from commit 797a615357
)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
parent
8eb4704b12
commit
fd6fe087ca
10 changed files with 43 additions and 58 deletions
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@ -74,7 +74,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
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* not rely on its state.
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*/
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intel_gt_suspend(&i915->gt);
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intel_uc_suspend(&i915->gt.uc);
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i915_gem_drain_freed_objects(i915);
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}
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@ -140,8 +139,6 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
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list_splice_tail(&keep, *phase);
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}
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spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
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i915_gem_sanitize(i915);
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}
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void i915_gem_resume(struct drm_i915_private *i915)
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@ -161,8 +158,6 @@ void i915_gem_resume(struct drm_i915_private *i915)
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if (intel_gt_resume(&i915->gt))
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goto err_wedged;
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intel_uc_resume(&i915->gt.uc);
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/* Always reload a context for powersaving. */
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if (!switch_to_kernel_context_sync(&i915->gt))
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goto err_wedged;
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@ -31,9 +31,11 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
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intel_uc_init_early(>->uc);
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}
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void intel_gt_init_hw_early(struct drm_i915_private *i915)
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void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
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{
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i915->gt.ggtt = &i915->ggtt;
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gt->ggtt = ggtt;
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intel_gt_sanitize(gt, false);
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}
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static void init_unused_ring(struct intel_gt *gt, u32 base)
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@ -28,7 +28,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
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}
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void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
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void intel_gt_init_hw_early(struct drm_i915_private *i915);
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void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
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int __must_check intel_gt_init_hw(struct intel_gt *gt);
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int intel_gt_init(struct intel_gt *gt);
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void intel_gt_driver_register(struct intel_gt *gt);
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@ -118,8 +118,22 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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GEM_TRACE("\n");
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GEM_TRACE("force:%s\n", yesno(force));
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/* Use a raw wakeref to avoid calling intel_display_power_get early */
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wakeref = intel_runtime_pm_get(gt->uncore->rpm);
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intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
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/*
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* As we have just resumed the machine and woken the device up from
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* deep PCI sleep (presumably D3_cold), assume the HW has been reset
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* back to defaults, recovering from whatever wedged state we left it
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* in and so worth trying to use the device once more.
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*/
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if (intel_gt_is_wedged(gt))
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intel_gt_unset_wedged(gt);
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intel_uc_sanitize(>->uc);
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@ -127,6 +141,8 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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if (engine->reset.prepare)
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engine->reset.prepare(engine);
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intel_uc_reset_prepare(>->uc);
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if (reset_engines(gt) || force) {
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for_each_engine(engine, gt, id)
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__intel_engine_reset(engine, false);
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@ -135,6 +151,9 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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for_each_engine(engine, gt, id)
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if (engine->reset.finish)
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engine->reset.finish(engine);
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intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(gt->uncore->rpm, wakeref);
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}
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void intel_gt_pm_fini(struct intel_gt *gt)
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@ -148,6 +167,8 @@ int intel_gt_resume(struct intel_gt *gt)
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enum intel_engine_id id;
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int err = 0;
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GEM_TRACE("\n");
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/*
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* After resume, we may need to poke into the pinned kernel
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* contexts to paper over any damage caused by the sudden suspend.
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@ -186,6 +207,9 @@ int intel_gt_resume(struct intel_gt *gt)
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}
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intel_rc6_enable(>->rc6);
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intel_uc_resume(>->uc);
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intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
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intel_gt_pm_put(gt);
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@ -212,20 +236,30 @@ void intel_gt_suspend(struct intel_gt *gt)
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/* We expect to be idle already; but also want to be independent */
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wait_for_idle(gt);
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intel_uc_suspend(>->uc);
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with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
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intel_rps_disable(>->rps);
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intel_rc6_disable(>->rc6);
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intel_llc_disable(>->llc);
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}
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intel_gt_sanitize(gt, false);
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GEM_TRACE("\n");
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}
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void intel_gt_runtime_suspend(struct intel_gt *gt)
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{
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intel_uc_runtime_suspend(>->uc);
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GEM_TRACE("\n");
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}
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int intel_gt_runtime_resume(struct intel_gt *gt)
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{
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GEM_TRACE("\n");
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intel_gt_init_swizzling(gt);
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return intel_uc_runtime_resume(>->uc);
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@ -603,8 +603,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
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if (ret)
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goto err_uncore;
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i915_gem_init_mmio(dev_priv);
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return 0;
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err_uncore:
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@ -1177,7 +1175,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
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if (ret)
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goto err_ggtt;
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intel_gt_init_hw_early(dev_priv);
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intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
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ret = i915_ggtt_enable_hw(dev_priv);
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if (ret) {
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@ -1821,7 +1819,7 @@ static int i915_drm_resume(struct drm_device *dev)
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disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
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i915_gem_sanitize(dev_priv);
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intel_gt_sanitize(&dev_priv->gt, true);
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ret = i915_ggtt_enable_hw(dev_priv);
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if (ret)
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@ -1952,8 +1950,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
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intel_power_domains_resume(dev_priv);
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intel_gt_sanitize(&dev_priv->gt, true);
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enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
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return ret;
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@ -1779,7 +1779,6 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
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/* i915_gem.c */
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int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
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void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
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void i915_gem_sanitize(struct drm_i915_private *i915);
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void i915_gem_init_early(struct drm_i915_private *dev_priv);
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void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
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int i915_gem_freeze(struct drm_i915_private *dev_priv);
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@ -1863,7 +1862,6 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
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return atomic_read(&error->reset_engine_count[engine->uabi_class]);
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}
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void i915_gem_init_mmio(struct drm_i915_private *i915);
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int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
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void i915_gem_driver_register(struct drm_i915_private *i915);
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void i915_gem_driver_unregister(struct drm_i915_private *i915);
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@ -1039,38 +1039,6 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
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return err;
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}
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void i915_gem_sanitize(struct drm_i915_private *i915)
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{
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intel_wakeref_t wakeref;
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GEM_TRACE("\n");
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wakeref = intel_runtime_pm_get(&i915->runtime_pm);
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intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
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/*
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* As we have just resumed the machine and woken the device up from
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* deep PCI sleep (presumably D3_cold), assume the HW has been reset
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* back to defaults, recovering from whatever wedged state we left it
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* in and so worth trying to use the device once more.
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*/
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if (intel_gt_is_wedged(&i915->gt))
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intel_gt_unset_wedged(&i915->gt);
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/*
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* If we inherit context state from the BIOS or earlier occupants
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* of the GPU, the GPU may be in an inconsistent state when we
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* try to take over. The only way to remove the earlier state
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* is by resetting. However, resetting on earlier gen is tricky as
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* it may impact the display and we are uncertain about the stability
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* of the reset, so this could be applied to even earlier gen.
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*/
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intel_gt_sanitize(&i915->gt, false);
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(&i915->runtime_pm, wakeref);
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}
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static int __intel_engines_record_defaults(struct intel_gt *gt)
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{
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struct i915_request *requests[I915_NUM_ENGINES] = {};
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@ -1413,11 +1381,6 @@ void i915_gem_driver_release(struct drm_i915_private *dev_priv)
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WARN_ON(!list_empty(&dev_priv->gem.contexts.list));
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}
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void i915_gem_init_mmio(struct drm_i915_private *i915)
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{
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i915_gem_sanitize(i915);
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}
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static void i915_gem_init__mm(struct drm_i915_private *i915)
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{
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spin_lock_init(&i915->mm.obj_lock);
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@ -124,7 +124,6 @@ static void pm_resume(struct drm_i915_private *i915)
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*/
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with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
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intel_gt_sanitize(&i915->gt, false);
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i915_gem_sanitize(i915);
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i915_gem_restore_gtt_mappings(i915);
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i915_gem_restore_fences(&i915->ggtt);
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@ -183,7 +183,6 @@ struct drm_i915_private *mock_gem_device(void)
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intel_timelines_init(i915);
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mock_init_ggtt(i915, &i915->ggtt);
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i915->gt.ggtt = &i915->ggtt;
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mkwrite_device_info(i915)->engine_mask = BIT(0);
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@ -118,8 +118,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
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ggtt->vm.vma_ops.clear_pages = clear_pages;
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i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
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intel_gt_init_hw_early(i915);
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i915->gt.ggtt = ggtt;
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}
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void mock_fini_ggtt(struct i915_ggtt *ggtt)
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