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x86/amd-iommu: Add ATS enable/disable code
This patch adds the necessary code to the AMD IOMMU driver for enabling and disabling the ATS capability on a device and to setup the IOMMU data structures correctly. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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parent
60f723b411
commit
fd7b5535e1
2 changed files with 30 additions and 6 deletions
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@ -216,6 +216,8 @@
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#define IOMMU_PTE_IR (1ULL << 61)
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#define IOMMU_PTE_IW (1ULL << 62)
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#define DTE_FLAG_IOTLB 0x01
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#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
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#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
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@ -1452,17 +1452,22 @@ static bool dma_ops_domain(struct protection_domain *domain)
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return domain->flags & PD_DMA_OPS_MASK;
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}
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static void set_dte_entry(u16 devid, struct protection_domain *domain)
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static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
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{
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u64 pte_root = virt_to_phys(domain->pt_root);
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u32 flags = 0;
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pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
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<< DEV_ENTRY_MODE_SHIFT;
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pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
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amd_iommu_dev_table[devid].data[2] = domain->id;
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amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
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amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
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if (ats)
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flags |= DTE_FLAG_IOTLB;
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amd_iommu_dev_table[devid].data[3] |= flags;
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amd_iommu_dev_table[devid].data[2] = domain->id;
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amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
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amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
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}
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static void clear_dte_entry(u16 devid)
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@ -1479,16 +1484,22 @@ static void do_attach(struct device *dev, struct protection_domain *domain)
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{
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struct iommu_dev_data *dev_data;
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struct amd_iommu *iommu;
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struct pci_dev *pdev;
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bool ats = false;
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u16 devid;
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devid = get_device_id(dev);
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iommu = amd_iommu_rlookup_table[devid];
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dev_data = get_dev_data(dev);
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pdev = to_pci_dev(dev);
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if (amd_iommu_iotlb_sup)
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ats = pci_ats_enabled(pdev);
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/* Update data structures */
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dev_data->domain = domain;
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list_add(&dev_data->list, &domain->dev_list);
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set_dte_entry(devid, domain);
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set_dte_entry(devid, domain, ats);
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/* Do reference counting */
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domain->dev_iommu[iommu->index] += 1;
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@ -1502,11 +1513,13 @@ static void do_detach(struct device *dev)
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{
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struct iommu_dev_data *dev_data;
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struct amd_iommu *iommu;
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struct pci_dev *pdev;
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u16 devid;
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devid = get_device_id(dev);
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iommu = amd_iommu_rlookup_table[devid];
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dev_data = get_dev_data(dev);
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pdev = to_pci_dev(dev);
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/* decrease reference counters */
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dev_data->domain->dev_iommu[iommu->index] -= 1;
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@ -1581,9 +1594,13 @@ static int __attach_device(struct device *dev,
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static int attach_device(struct device *dev,
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struct protection_domain *domain)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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unsigned long flags;
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int ret;
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if (amd_iommu_iotlb_sup)
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pci_enable_ats(pdev, PAGE_SHIFT);
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write_lock_irqsave(&amd_iommu_devtable_lock, flags);
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ret = __attach_device(dev, domain);
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write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
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@ -1640,12 +1657,16 @@ static void __detach_device(struct device *dev)
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*/
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static void detach_device(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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unsigned long flags;
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/* lock device table */
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write_lock_irqsave(&amd_iommu_devtable_lock, flags);
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__detach_device(dev);
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write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
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if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev))
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pci_disable_ats(pdev);
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}
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/*
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@ -1795,8 +1816,9 @@ static void update_device_table(struct protection_domain *domain)
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struct iommu_dev_data *dev_data;
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list_for_each_entry(dev_data, &domain->dev_list, list) {
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struct pci_dev *pdev = to_pci_dev(dev_data->dev);
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u16 devid = get_device_id(dev_data->dev);
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set_dte_entry(devid, domain);
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set_dte_entry(devid, domain, pci_ats_enabled(pdev));
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}
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}
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