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drm/amd/display: Fix OTG disable workaround logic
[Why] DENTIST was hanging when performing DISPCLK update with OTG enabled, as OTG disable workaround was not executing. [How] Workaround was checking against current_state before running, but when called from optimize_bandwidth (safe_to_lower), we should be checking against context instead. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 7 additions and 4 deletions
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@ -111,13 +111,16 @@ static int dcn35_get_active_display_cnt_wa(
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return display_count;
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}
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static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
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static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
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bool safe_to_lower, bool disable)
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{
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struct dc *dc = clk_mgr_base->ctx->dc;
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; ++i) {
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struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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struct pipe_ctx *pipe = safe_to_lower
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? &context->res_ctx.pipe_ctx[i]
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: &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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continue;
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@ -301,11 +304,11 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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}
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
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dcn35_disable_otg_wa(clk_mgr_base, context, true);
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dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
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dcn35_disable_otg_wa(clk_mgr_base, context, false);
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dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
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update_dispclk = true;
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}
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