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clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
There are a few issues with the setup of the Actions Semi Owl S500 SoC's
clock chain involving AHPPREDIV, H and AHB clocks:
* AHBPREDIV clock is defined as a muxer only, although it also acts as
a divider.
* H clock is using a wrong divider register offset
* AHB is defined as a multi-rate factor clock, but it is actually just
a fixed pass clock.
Let's provide the following fixes:
* Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
* Use the correct register shift value in the OWL_DIVIDER definition
for H clock
* Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
ungated OWL_COMP_FIXED_FACTOR definition.
Fixes: ed6b4795ec
("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Link: https://lore.kernel.org/r/21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
a8f1f03caa
commit
fd90b5b904
1 changed files with 11 additions and 8 deletions
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@ -153,11 +153,6 @@ static struct clk_factor_table hde_factor_table[] = {
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{ 0, 0, 0 },
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{ 0, 0, 0 },
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};
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};
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static struct clk_factor_table ahb_factor_table[] = {
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{ 1, 1, 2 }, { 2, 1, 3 },
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{ 0, 0, 0 },
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};
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static struct clk_div_table rmii_ref_div_table[] = {
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static struct clk_div_table rmii_ref_div_table[] = {
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{ 0, 4 }, { 1, 10 },
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{ 0, 4 }, { 1, 10 },
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{ 0, 0 },
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{ 0, 0 },
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@ -186,7 +181,6 @@ static struct clk_div_table nand_div_table[] = {
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/* mux clock */
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/* mux clock */
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static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
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static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
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static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
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/* gate clocks */
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/* gate clocks */
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static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
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static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
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@ -199,16 +193,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
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static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
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static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
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/* divider clocks */
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/* divider clocks */
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static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
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static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
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static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
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static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
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static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
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static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
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/* factor clocks */
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/* factor clocks */
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static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
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static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
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static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
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static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
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static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
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/* composite clocks */
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/* composite clocks */
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static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
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OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
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{ 0 },
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OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
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CLK_SET_RATE_PARENT);
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static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
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{ 0 },
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1, 1, 0);
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static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
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static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
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OWL_MUX_HW(CMU_VCECLK, 4, 2),
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OWL_MUX_HW(CMU_VCECLK, 4, 2),
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OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
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OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
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