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pmic wrapper:
- add support for MT6779 SoC cmdq-helper: - set knows_txdone in mailbox client -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl50pW8XHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH67Aw/+IZlwFvspiqJTCujacHquxvIb 6BfgGs0v1Byv2cySLVianZbtc1mvWk8gS9ODdtcRvDTE3aQsyDm4Qmn8cWxa/VsA +uUf1m7aS9ec5MQUN7TOyX44WyePw/gndtcnvlX0gsB9fl1DnYoEcSokXxxpARvg RYuxG0Isyw3cr8ybWf4BgO2zsrfFKZ+z2YWp8aY74/V5JZdTUbHBQ2XxfInyXka8 VUaGwIH7QfYJUNa6m6DmEsFro47Gy1Jq4DZAz6pIae5lIAfd53G9KWlfwz4VI06v l41/HYKWEd/qRVnBPY7K6wOTl7aSAWWQCdaWaFVqu9m7C3PxLgNv0txgubAb7cI5 uUvBGh+mgdfJYS9rlfzWvRFFpGXpsaO8JXxo5+sqin9xy8tP3GiYvDlsXaYXLFVk KpLbGdTmd2wQOQEW4pubck4gzSBwgCP51R5L9iU1SiVT3Tod7RriEUtU+noTQUGA CeEwUhnnsSDzKv/5iEhDXAFW2Va6Q7YaEvRzw4PuneF56XF2SClGWmpe4PLtJuw7 Szwo3fiq+NqbKJoa5KYQvbheiXZN8fADc1o7JkUTp/hvHBcixjUV3kCqGeJ2xR/z +MU4kX1FCgugBlMZzOA7l6rHVJaK0jjItqFNy8Q4IqQGZ2FyJPl46XPFV1W1h23L F0RNdxarsXGbXN63V3c= =+JxZ -----END PGP SIGNATURE----- Merge tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/soc pmic wrapper: - add support for MT6779 SoC cmdq-helper: - set knows_txdone in mailbox client * tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: pwrap: add support for MT6359 PMIC soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs dt-bindings: pwrap: mediatek: add pwrap support for MT6779 soc: mediatek: knows_txdone needs to be set in Mediatek CMDQ helper Link: https://lore.kernel.org/r/61165e91-f211-ad37-a81c-cbf3ff69fa1b@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
fd91e03e5f
3 changed files with 130 additions and 0 deletions
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@ -20,6 +20,7 @@ Required properties in pwrap device node.
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- compatible:
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"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
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"mediatek,mt6765-pwrap" for MT6765 SoCs
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"mediatek,mt6779-pwrap" for MT6779 SoCs
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"mediatek,mt6797-pwrap" for MT6797 SoCs
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"mediatek,mt7622-pwrap" for MT7622 SoCs
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"mediatek,mt8135-pwrap" for MT8135 SoCs
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@ -78,6 +78,7 @@ struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout)
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client->pkt_cnt = 0;
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client->client.dev = dev;
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client->client.tx_block = false;
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client->client.knows_txdone = true;
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client->chan = mbox_request_channel(&client->client, index);
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if (IS_ERR(client->chan)) {
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@ -111,6 +111,28 @@ enum dew_regs {
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PWRAP_RG_SPI_CON13,
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PWRAP_SPISLV_KEY,
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/* MT6359 only regs */
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PWRAP_DEW_CRC_SWRST,
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PWRAP_DEW_RG_EN_RECORD,
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PWRAP_DEW_RECORD_CMD0,
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PWRAP_DEW_RECORD_CMD1,
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PWRAP_DEW_RECORD_CMD2,
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PWRAP_DEW_RECORD_CMD3,
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PWRAP_DEW_RECORD_CMD4,
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PWRAP_DEW_RECORD_CMD5,
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PWRAP_DEW_RECORD_WDATA0,
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PWRAP_DEW_RECORD_WDATA1,
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PWRAP_DEW_RECORD_WDATA2,
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PWRAP_DEW_RECORD_WDATA3,
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PWRAP_DEW_RECORD_WDATA4,
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PWRAP_DEW_RECORD_WDATA5,
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PWRAP_DEW_RG_ADDR_TARGET,
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PWRAP_DEW_RG_ADDR_MASK,
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PWRAP_DEW_RG_WDATA_TARGET,
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PWRAP_DEW_RG_WDATA_MASK,
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PWRAP_DEW_RG_SPI_RECORD_CLR,
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PWRAP_DEW_RG_CMD_ALERT_CLR,
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/* MT6397 only regs */
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PWRAP_DEW_EVENT_OUT_EN,
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PWRAP_DEW_EVENT_SRC_EN,
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@ -197,6 +219,42 @@ static const u32 mt6358_regs[] = {
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[PWRAP_SPISLV_KEY] = 0x044a,
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};
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static const u32 mt6359_regs[] = {
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[PWRAP_DEW_RG_EN_RECORD] = 0x040a,
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[PWRAP_DEW_DIO_EN] = 0x040c,
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[PWRAP_DEW_READ_TEST] = 0x040e,
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[PWRAP_DEW_WRITE_TEST] = 0x0410,
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[PWRAP_DEW_CRC_SWRST] = 0x0412,
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[PWRAP_DEW_CRC_EN] = 0x0414,
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[PWRAP_DEW_CRC_VAL] = 0x0416,
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[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
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[PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
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[PWRAP_DEW_CIPHER_EN] = 0x041c,
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[PWRAP_DEW_CIPHER_RDY] = 0x041e,
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[PWRAP_DEW_CIPHER_MODE] = 0x0420,
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[PWRAP_DEW_CIPHER_SWRST] = 0x0422,
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[PWRAP_DEW_RDDMY_NO] = 0x0424,
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[PWRAP_DEW_RECORD_CMD0] = 0x0428,
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[PWRAP_DEW_RECORD_CMD1] = 0x042a,
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[PWRAP_DEW_RECORD_CMD2] = 0x042c,
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[PWRAP_DEW_RECORD_CMD3] = 0x042e,
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[PWRAP_DEW_RECORD_CMD4] = 0x0430,
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[PWRAP_DEW_RECORD_CMD5] = 0x0432,
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[PWRAP_DEW_RECORD_WDATA0] = 0x0434,
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[PWRAP_DEW_RECORD_WDATA1] = 0x0436,
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[PWRAP_DEW_RECORD_WDATA2] = 0x0438,
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[PWRAP_DEW_RECORD_WDATA3] = 0x043a,
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[PWRAP_DEW_RECORD_WDATA4] = 0x043c,
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[PWRAP_DEW_RECORD_WDATA5] = 0x043e,
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[PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
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[PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
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[PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
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[PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
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[PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
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[PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
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[PWRAP_SPISLV_KEY] = 0x044a,
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};
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static const u32 mt6397_regs[] = {
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[PWRAP_DEW_BASE] = 0xbc00,
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[PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
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@ -497,6 +555,45 @@ static int mt6765_regs[] = {
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[PWRAP_DCM_DBC_PRD] = 0x1E0,
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};
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static int mt6779_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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[PWRAP_DIO_EN] = 0x8,
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[PWRAP_RDDMY] = 0x20,
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[PWRAP_CSHEXT_WRITE] = 0x24,
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[PWRAP_CSHEXT_READ] = 0x28,
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[PWRAP_CSLEXT_WRITE] = 0x2C,
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[PWRAP_CSLEXT_READ] = 0x30,
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[PWRAP_EXT_CK_WRITE] = 0x34,
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[PWRAP_STAUPD_CTRL] = 0x3C,
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[PWRAP_STAUPD_GRPEN] = 0x40,
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[PWRAP_EINT_STA0_ADR] = 0x44,
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[PWRAP_HARB_HPRIO] = 0x68,
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[PWRAP_HIPRIO_ARB_EN] = 0x6C,
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[PWRAP_MAN_EN] = 0x7C,
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[PWRAP_MAN_CMD] = 0x80,
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[PWRAP_WACS0_EN] = 0x8C,
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[PWRAP_INIT_DONE0] = 0x90,
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[PWRAP_WACS1_EN] = 0x94,
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[PWRAP_WACS2_EN] = 0x9C,
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[PWRAP_INIT_DONE1] = 0x98,
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[PWRAP_INIT_DONE2] = 0xA0,
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[PWRAP_INT_EN] = 0xBC,
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[PWRAP_INT_FLG_RAW] = 0xC0,
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[PWRAP_INT_FLG] = 0xC4,
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[PWRAP_INT_CLR] = 0xC8,
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[PWRAP_INT1_EN] = 0xCC,
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[PWRAP_INT1_FLG] = 0xD4,
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[PWRAP_INT1_CLR] = 0xD8,
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[PWRAP_TIMER_EN] = 0xF0,
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[PWRAP_WDT_UNIT] = 0xF8,
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[PWRAP_WDT_SRC_EN] = 0xFC,
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[PWRAP_WDT_SRC_EN_1] = 0x100,
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[PWRAP_WACS2_CMD] = 0xC20,
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[PWRAP_WACS2_RDATA] = 0xC24,
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[PWRAP_WACS2_VLDCLR] = 0xC28,
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};
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static int mt6797_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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@ -938,6 +1035,7 @@ enum pmic_type {
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PMIC_MT6351,
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PMIC_MT6357,
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PMIC_MT6358,
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PMIC_MT6359,
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PMIC_MT6380,
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PMIC_MT6397,
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};
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@ -945,6 +1043,7 @@ enum pmic_type {
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enum pwrap_type {
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PWRAP_MT2701,
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PWRAP_MT6765,
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PWRAP_MT6779,
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PWRAP_MT6797,
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PWRAP_MT7622,
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PWRAP_MT8135,
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@ -1377,6 +1476,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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break;
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case PWRAP_MT2701:
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case PWRAP_MT6765:
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case PWRAP_MT6779:
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case PWRAP_MT6797:
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case PWRAP_MT8173:
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case PWRAP_MT8516:
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@ -1711,6 +1811,15 @@ static const struct pwrap_slv_type pmic_mt6358 = {
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.pwrap_write = pwrap_write16,
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};
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static const struct pwrap_slv_type pmic_mt6359 = {
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.dew_regs = mt6359_regs,
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.type = PMIC_MT6359,
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.regmap = &pwrap_regmap_config16,
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.caps = PWRAP_SLV_CAP_DUALIO,
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.pwrap_read = pwrap_read16,
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.pwrap_write = pwrap_write16,
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};
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static const struct pwrap_slv_type pmic_mt6380 = {
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.dew_regs = NULL,
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.type = PMIC_MT6380,
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@ -1743,6 +1852,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt6358",
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.data = &pmic_mt6358,
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}, {
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.compatible = "mediatek,mt6359",
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.data = &pmic_mt6359,
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}, {
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/* The MT6380 PMIC only implements a regulator, so we bind it
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* directly instead of using a MFD.
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@ -1783,6 +1895,19 @@ static const struct pmic_wrapper_type pwrap_mt6765 = {
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.init_soc_specific = NULL,
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};
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static const struct pmic_wrapper_type pwrap_mt6779 = {
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.regs = mt6779_regs,
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.type = PWRAP_MT6779,
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.arb_en_all = 0xfbb7f,
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.int_en_all = 0xfffffffe,
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = 0,
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.init_reg_clock = pwrap_common_init_reg_clock,
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.init_soc_specific = NULL,
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};
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static const struct pmic_wrapper_type pwrap_mt6797 = {
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.regs = mt6797_regs,
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.type = PWRAP_MT6797,
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@ -1867,6 +1992,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt6765-pwrap",
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.data = &pwrap_mt6765,
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}, {
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.compatible = "mediatek,mt6779-pwrap",
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.data = &pwrap_mt6779,
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}, {
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.compatible = "mediatek,mt6797-pwrap",
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.data = &pwrap_mt6797,
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