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phy: qcom-qmp-pcie: cleanup the driver
Remove the conditionals and options that are not used by any of PCIe PHY devices. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-21-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
parent
6066bac15b
commit
fd9269945f
1 changed files with 11 additions and 202 deletions
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@ -1257,22 +1257,6 @@ struct qmp_phy_cfg {
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const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
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int pcs_misc_tbl_num_sec;
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/* Init sequence for DP PHY block link rates */
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const struct qmp_phy_init_tbl *serdes_tbl_rbr;
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int serdes_tbl_rbr_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr;
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int serdes_tbl_hbr_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
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int serdes_tbl_hbr2_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
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int serdes_tbl_hbr3_num;
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/* DP PHY callbacks */
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int (*configure_dp_phy)(struct qmp_phy *qphy);
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void (*configure_dp_tx)(struct qmp_phy *qphy);
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int (*calibrate_dp_phy)(struct qmp_phy *qphy);
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void (*dp_aux_init)(struct qmp_phy *qphy);
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/* clock ids to be requested */
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const char * const *clk_list;
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int num_clks;
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@ -1292,28 +1276,14 @@ struct qmp_phy_cfg {
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/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
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unsigned int phy_status;
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/* true, if PHY has a separate PHY_COM control block */
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bool has_phy_com_ctrl;
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/* true, if PHY has a reset for individual lanes */
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bool has_lane_rst;
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/* true, if PHY needs delay after POWER_DOWN */
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bool has_pwrdn_delay;
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/* power_down delay in usec */
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int pwrdn_delay_min;
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int pwrdn_delay_max;
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/* true, if PHY has a separate DP_COM control block */
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bool has_phy_dp_com_ctrl;
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/* true, if PHY has secondary tx/rx lanes to be configured */
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bool is_dual_lane_phy;
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/* true, if PCS block has no separate SW_RESET register */
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bool no_pcs_sw_reset;
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};
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struct qmp_phy_combo_cfg {
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const struct qmp_phy_cfg *usb_cfg;
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const struct qmp_phy_cfg *dp_cfg;
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};
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/**
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@ -1331,11 +1301,7 @@ struct qmp_phy_combo_cfg {
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* @pipe_clk: pipe clock
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* @index: lane index
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* @qmp: QMP phy to which this lane belongs
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* @lane_rst: lane's reset controller
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* @mode: current PHY mode
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* @dp_aux_cfg: Display port aux config
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* @dp_opts: Display port optional config
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* @dp_clks: Display port clocks
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*/
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struct qmp_phy {
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struct phy *phy;
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@ -1350,24 +1316,13 @@ struct qmp_phy {
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struct clk *pipe_clk;
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unsigned int index;
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struct qcom_qmp *qmp;
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struct reset_control *lane_rst;
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enum phy_mode mode;
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unsigned int dp_aux_cfg;
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struct phy_configure_opts_dp dp_opts;
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struct qmp_phy_dp_clks *dp_clks;
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};
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struct qmp_phy_dp_clks {
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struct qmp_phy *qphy;
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struct clk_hw dp_link_hw;
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struct clk_hw dp_pixel_hw;
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};
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/**
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* struct qcom_qmp - structure holding QMP phy block attributes
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*
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* @dev: device
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* @dp_com: iomapped memory space for phy's dp_com control block
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*
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* @clks: array of clocks required by phy
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* @resets: array of resets required by phy
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@ -1376,11 +1331,9 @@ struct qmp_phy_dp_clks {
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* @phys: array of per-lane phy descriptors
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* @phy_mutex: mutex lock for PHY common block initialization
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* @init_count: phy common block initialization count
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* @ufs_reset: optional UFS PHY reset handle
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*/
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struct qcom_qmp {
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struct device *dev;
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void __iomem *dp_com;
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struct clk_bulk_data *clks;
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struct reset_control **resets;
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@ -1390,8 +1343,6 @@ struct qcom_qmp {
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struct mutex phy_mutex;
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int init_count;
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struct reset_control *ufs_reset;
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};
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static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
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@ -1470,8 +1421,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS,
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.has_phy_com_ctrl = false,
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.has_lane_rst = false,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = 995, /* us */
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.pwrdn_delay_max = 1005, /* us */
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@ -1500,8 +1449,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.has_phy_com_ctrl = false,
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.has_lane_rst = false,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = 995, /* us */
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.pwrdn_delay_max = 1005, /* us */
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@ -1829,38 +1776,16 @@ static void qcom_qmp_phy_pcie_configure(void __iomem *base,
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static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
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int serdes_tbl_num = cfg->serdes_tbl_num;
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int ret;
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
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if (cfg->serdes_tbl_sec)
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
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cfg->serdes_tbl_num_sec);
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if (cfg->has_phy_com_ctrl) {
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void __iomem *status;
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unsigned int mask, val;
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
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mask = cfg->mask_com_pcs_ready;
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ret = readl_poll_timeout(status, val, (val & mask), 10,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev,
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"phy common block init timed-out\n");
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return ret;
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}
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}
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return 0;
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}
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@ -1868,9 +1793,7 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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void __iomem *pcs = qphy->pcs;
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void __iomem *dp_com = qmp->dp_com;
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int ret, i;
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mutex_lock(&qmp->phy_mutex);
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@ -1908,41 +1831,13 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
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if (ret)
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goto err_assert_reset;
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if (cfg->has_phy_dp_com_ctrl) {
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qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
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SW_PWRDN);
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/* override hardware control for reset of qmp phy */
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qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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/* Default type-c orientation, i.e CC1 */
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qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
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qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
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USB3_MODE | DP_MODE);
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/* bring both QMP USB and QMP DP PHYs PCS block out of reset */
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
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}
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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} else {
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
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qphy_setbits(pcs,
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cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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else
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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}
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
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qphy_setbits(pcs,
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cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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else
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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mutex_unlock(&qmp->phy_mutex);
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@ -1963,7 +1858,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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int i = cfg->num_resets;
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mutex_lock(&qmp->phy_mutex);
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@ -1972,16 +1866,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy)
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return 0;
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}
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reset_control_assert(qmp->ufs_reset);
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
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SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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}
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while (--i >= 0)
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reset_control_assert(qmp->resets[i]);
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@ -1998,37 +1882,9 @@ static int qcom_qmp_phy_pcie_init(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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int ret;
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dev_vdbg(qmp->dev, "Initializing QMP phy\n");
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if (cfg->no_pcs_sw_reset) {
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/*
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* Get UFS reset, which is delayed until now to avoid a
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* circular dependency where UFS needs its PHY, but the PHY
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* needs this UFS reset.
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*/
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if (!qmp->ufs_reset) {
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qmp->ufs_reset =
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devm_reset_control_get_exclusive(qmp->dev,
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"ufsphy");
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if (IS_ERR(qmp->ufs_reset)) {
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ret = PTR_ERR(qmp->ufs_reset);
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dev_err(qmp->dev,
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"failed to get UFS reset: %d\n",
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ret);
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qmp->ufs_reset = NULL;
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return ret;
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}
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}
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ret = reset_control_assert(qmp->ufs_reset);
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if (ret)
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return ret;
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}
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ret = qcom_qmp_phy_pcie_com_init(qphy);
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if (ret)
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return ret;
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@ -2051,19 +1907,10 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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qcom_qmp_phy_pcie_serdes_init(qphy);
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if (cfg->has_lane_rst) {
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ret = reset_control_deassert(qphy->lane_rst);
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if (ret) {
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dev_err(qmp->dev, "lane%d reset deassert failed\n",
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qphy->index);
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return ret;
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}
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}
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ret = clk_prepare_enable(qphy->pipe_clk);
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if (ret) {
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dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
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goto err_reset_lane;
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return ret;
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}
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/* Tx, Rx, and PCS configurations */
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@ -2103,10 +1950,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
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cfg->pcs_tbl_num_sec);
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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goto err_disable_pipe_clk;
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qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
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cfg->pcs_misc_tbl_num);
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if (cfg->pcs_misc_tbl_sec)
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@ -2123,8 +1966,8 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
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/* Pull PHY out of reset state */
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if (!cfg->no_pcs_sw_reset)
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* start SerDes and Phy-Coding-Sublayer */
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qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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@ -2143,9 +1986,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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err_disable_pipe_clk:
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clk_disable_unprepare(qphy->pipe_clk);
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err_reset_lane:
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if (cfg->has_lane_rst)
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reset_control_assert(qphy->lane_rst);
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return ret;
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}
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@ -2158,8 +1998,7 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
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clk_disable_unprepare(qphy->pipe_clk);
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/* PHY reset */
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if (!cfg->no_pcs_sw_reset)
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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@ -2179,10 +2018,6 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
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static int qcom_qmp_phy_pcie_exit(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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if (cfg->has_lane_rst)
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reset_control_assert(qphy->lane_rst);
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qcom_qmp_phy_pcie_com_exit(qphy);
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@ -2348,11 +2183,6 @@ static const struct phy_ops qcom_qmp_phy_pcie_ops = {
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.owner = THIS_MODULE,
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};
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static void qcom_qmp_reset_control_put(void *data)
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{
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reset_control_put(data);
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}
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static
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int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
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void __iomem *serdes, const struct qmp_phy_cfg *cfg)
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@ -2438,20 +2268,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
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qphy->pipe_clk = NULL;
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}
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/* Get lane reset, if any */
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if (cfg->has_lane_rst) {
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snprintf(prop_name, sizeof(prop_name), "lane%d", id);
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qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
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if (IS_ERR(qphy->lane_rst)) {
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dev_err(dev, "failed to get lane%d reset\n", id);
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return PTR_ERR(qphy->lane_rst);
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}
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ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
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qphy->lane_rst);
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if (ret)
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return ret;
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}
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generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops);
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if (IS_ERR(generic_phy)) {
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ret = PTR_ERR(generic_phy);
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@ -2538,13 +2354,6 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(serdes))
|
||||
return PTR_ERR(serdes);
|
||||
|
||||
/* per PHY dp_com; if PHY has dp_com control block */
|
||||
if (cfg->has_phy_dp_com_ctrl) {
|
||||
qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(qmp->dp_com))
|
||||
return PTR_ERR(qmp->dp_com);
|
||||
}
|
||||
|
||||
expected_phys = cfg->nlanes;
|
||||
|
||||
mutex_init(&qmp->phy_mutex);
|
||||
|
|
|
|||
Loading…
Reference in a new issue