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drm/amd/display: Workaround for some legacy DP-VGA dongles
[Why] Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and this leads to the maximum resolution 1920*1080 cannot be obtained from EDID. [How] Provide a workaround for some legacy DP-VGA dongles with a longer aux delay. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 12 additions and 1 deletions
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@ -39,12 +39,14 @@
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#define DC_LOGGER_INIT(logger)
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/*DP to Dual link DVI converter*/
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static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
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/* DP to Dual link DVI converter */
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static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
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static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
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#define AUX_POWER_UP_WA_DELAY 500
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#define I2C_OVER_AUX_DEFER_WA_DELAY 70
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#define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40
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#define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
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/* CV smart dongle slave address for retrieving supported HDTV modes*/
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@ -292,6 +294,15 @@ static uint32_t defer_delay_converter_wa(
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{
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struct dc_link *link = ddc->link;
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if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
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link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
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!memcmp(link->dpcd_caps.branch_dev_name,
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DP_VGA_DONGLE_BRANCH_DEV_NAME,
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sizeof(link->dpcd_caps.branch_dev_name)))
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return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
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defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
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if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
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!memcmp(link->dpcd_caps.branch_dev_name,
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DP_DVI_CONVERTER_ID_4,
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