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clocksource: exynos_mct: Use readl_relaxed/writel_relaxed
Using the __raw functions is discouraged. Update the file to consistently use the proper functions. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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a38b1f60b5
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1 changed files with 12 additions and 12 deletions
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@ -94,7 +94,7 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
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u32 mask;
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u32 mask;
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u32 i;
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u32 i;
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__raw_writel(value, reg_base + offset);
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writel_relaxed(value, reg_base + offset);
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if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
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if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
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stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
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stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
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@ -144,8 +144,8 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
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/* Wait maximum 1 ms until written values are applied */
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/* Wait maximum 1 ms until written values are applied */
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for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
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for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
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if (__raw_readl(reg_base + stat_addr) & mask) {
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if (readl_relaxed(reg_base + stat_addr) & mask) {
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__raw_writel(mask, reg_base + stat_addr);
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writel_relaxed(mask, reg_base + stat_addr);
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return;
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return;
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}
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}
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@ -157,7 +157,7 @@ static void exynos4_mct_frc_start(void)
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{
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{
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u32 reg;
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u32 reg;
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reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
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reg |= MCT_G_TCON_START;
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reg |= MCT_G_TCON_START;
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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}
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}
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@ -165,12 +165,12 @@ static void exynos4_mct_frc_start(void)
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static cycle_t notrace _exynos4_frc_read(void)
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static cycle_t notrace _exynos4_frc_read(void)
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{
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{
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unsigned int lo, hi;
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unsigned int lo, hi;
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u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
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u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
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do {
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do {
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hi = hi2;
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hi = hi2;
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lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
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lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
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hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
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hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
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} while (hi != hi2);
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} while (hi != hi2);
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return ((cycle_t)hi << 32) | lo;
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return ((cycle_t)hi << 32) | lo;
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@ -225,7 +225,7 @@ static void exynos4_mct_comp0_stop(void)
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{
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{
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unsigned int tcon;
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unsigned int tcon;
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tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
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tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
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tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
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exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
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exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
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@ -238,7 +238,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
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unsigned int tcon;
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unsigned int tcon;
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cycle_t comp_cycle;
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cycle_t comp_cycle;
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tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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tcon |= MCT_G_TCON_COMP0_AUTO_INC;
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tcon |= MCT_G_TCON_COMP0_AUTO_INC;
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@ -327,7 +327,7 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
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unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
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unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
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unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
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unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
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tmp = __raw_readl(reg_base + offset);
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tmp = readl_relaxed(reg_base + offset);
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if (tmp & mask) {
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if (tmp & mask) {
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tmp &= ~mask;
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tmp &= ~mask;
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exynos4_mct_write(tmp, offset);
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exynos4_mct_write(tmp, offset);
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@ -349,7 +349,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
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/* enable MCT tick interrupt */
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/* enable MCT tick interrupt */
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
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tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
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tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
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tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
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tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
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MCT_L_TCON_INTERVAL_MODE;
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MCT_L_TCON_INTERVAL_MODE;
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exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
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exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
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@ -401,7 +401,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
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exynos4_mct_tick_stop(mevt);
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exynos4_mct_tick_stop(mevt);
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/* Clear the MCT tick interrupt */
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/* Clear the MCT tick interrupt */
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if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
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if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
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return 1;
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return 1;
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} else {
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} else {
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