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phy: ti-pipe3: improve DPLL stability for SATA & USB
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Roger Quadros
Kishon Vijay Abraham I
parent
22940823f0
commit
fdef2f9f70
1 changed files with 168 additions and 37 deletions
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@ -68,39 +68,61 @@
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#define PCIE_PCS_MASK 0xFF0000
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#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
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#define PCIEPHYRX_ANA_PROGRAMMABILITY 0x0000000C
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#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
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#define INTERFACE_MASK GENMASK(31, 27)
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#define INTERFACE_SHIFT 27
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#define INTERFACE_MODE_USBSS BIT(4)
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#define INTERFACE_MODE_SATA_1P5 BIT(3)
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#define INTERFACE_MODE_SATA_3P0 BIT(2)
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#define INTERFACE_MODE_PCIE BIT(0)
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#define LOSD_MASK GENMASK(17, 14)
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#define LOSD_SHIFT 14
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#define MEM_PLLDIV GENMASK(6, 5)
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#define PCIEPHYRX_TRIM 0x0000001C
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#define MEM_DLL_TRIM_SEL GENMASK(31, 30)
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#define PIPE3_PHY_RX_TRIM 0x0000001C
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#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
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#define MEM_DLL_TRIM_SHIFT 30
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#define PCIEPHYRX_DLL 0x00000024
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#define MEM_DLL_PHINT_RATE GENMASK(31, 30)
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#define PIPE3_PHY_RX_DLL 0x00000024
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#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
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#define MEM_DLL_PHINT_RATE_SHIFT 30
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#define PCIEPHYRX_DIGITAL_MODES 0x00000028
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#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
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#define MEM_HS_RATE_MASK GENMASK(28, 27)
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#define MEM_HS_RATE_SHIFT 27
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#define MEM_OVRD_HS_RATE BIT(26)
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#define MEM_OVRD_HS_RATE_SHIFT 26
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#define MEM_CDR_FASTLOCK BIT(23)
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#define MEM_CDR_LBW GENMASK(22, 21)
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#define MEM_CDR_STEPCNT GENMASK(20, 19)
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#define MEM_CDR_FASTLOCK_SHIFT 23
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#define MEM_CDR_LBW_MASK GENMASK(22, 21)
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#define MEM_CDR_LBW_SHIFT 21
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#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
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#define MEM_CDR_STEPCNT_SHIFT 19
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#define MEM_CDR_STL_MASK GENMASK(18, 16)
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#define MEM_CDR_STL_SHIFT 16
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#define MEM_CDR_THR_MASK GENMASK(15, 13)
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#define MEM_CDR_THR_SHIFT 13
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#define MEM_CDR_THR_MODE BIT(12)
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#define MEM_CDR_CDR_2NDO_SDM_MODE BIT(11)
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#define MEM_OVRD_HS_RATE BIT(26)
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#define MEM_CDR_THR_MODE_SHIFT 12
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#define MEM_CDR_2NDO_SDM_MODE BIT(11)
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#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
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#define PCIEPHYRX_EQUALIZER 0x00000038
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#define MEM_EQLEV GENMASK(31, 16)
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#define MEM_EQFTC GENMASK(15, 11)
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#define MEM_EQCTL GENMASK(10, 7)
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#define PIPE3_PHY_RX_EQUALIZER 0x00000038
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#define MEM_EQLEV_MASK GENMASK(31, 16)
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#define MEM_EQLEV_SHIFT 16
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#define MEM_EQFTC_MASK GENMASK(15, 11)
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#define MEM_EQFTC_SHIFT 11
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#define MEM_EQCTL_MASK GENMASK(10, 7)
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#define MEM_EQCTL_SHIFT 7
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#define MEM_OVRD_EQLEV BIT(2)
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#define MEM_OVRD_EQLEV_SHIFT 2
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#define MEM_OVRD_EQFTC BIT(1)
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#define MEM_OVRD_EQFTC_SHIFT 1
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#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
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#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
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#define MEM_CDR_LOS_SOURCE_SHIFT 9
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/*
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* This is an Empirical value that works, need to confirm the actual
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@ -127,6 +149,27 @@ struct pipe3_dpll_map {
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struct pipe3_dpll_params params;
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};
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struct pipe3_settings {
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u8 ana_interface;
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u8 ana_losd;
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u8 dig_fastlock;
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u8 dig_lbw;
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u8 dig_stepcnt;
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u8 dig_stl;
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u8 dig_thr;
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u8 dig_thr_mode;
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u8 dig_2ndo_sdm_mode;
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u8 dig_hs_rate;
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u8 dig_ovrd_hs_rate;
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u8 dll_trim_sel;
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u8 dll_phint_rate;
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u8 eq_lev;
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u8 eq_ftc;
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u8 eq_ctl;
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u8 eq_ovrd_lev;
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u8 eq_ovrd_ftc;
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};
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struct ti_pipe3 {
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void __iomem *pll_ctrl_base;
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void __iomem *phy_rx;
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@ -146,6 +189,7 @@ struct ti_pipe3 {
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unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
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bool sata_refclk_enabled;
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enum pipe3_mode mode;
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struct pipe3_settings settings;
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};
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static struct pipe3_dpll_map dpll_map_usb[] = {
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@ -171,20 +215,84 @@ static struct pipe3_dpll_map dpll_map_sata[] = {
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struct pipe3_data {
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enum pipe3_mode mode;
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struct pipe3_dpll_map *dpll_map;
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struct pipe3_settings settings;
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};
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static struct pipe3_data data_usb = {
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.mode = PIPE3_MODE_USBSS,
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.dpll_map = dpll_map_usb,
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.settings = {
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/* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
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.ana_interface = INTERFACE_MODE_USBSS,
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.ana_losd = 0xa,
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.dig_fastlock = 1,
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.dig_lbw = 3,
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.dig_stepcnt = 0,
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.dig_stl = 0x3,
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.dig_thr = 1,
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.dig_thr_mode = 1,
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.dig_2ndo_sdm_mode = 0,
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.dig_hs_rate = 0,
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.dig_ovrd_hs_rate = 1,
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.dll_trim_sel = 0x2,
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.dll_phint_rate = 0x3,
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.eq_lev = 0,
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.eq_ftc = 0,
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.eq_ctl = 0x9,
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.eq_ovrd_lev = 0,
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.eq_ovrd_ftc = 0,
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},
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};
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static struct pipe3_data data_sata = {
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.mode = PIPE3_MODE_SATA,
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.dpll_map = dpll_map_sata,
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.settings = {
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/* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
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.ana_interface = INTERFACE_MODE_SATA_3P0,
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.ana_losd = 0x5,
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.dig_fastlock = 1,
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.dig_lbw = 3,
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.dig_stepcnt = 0,
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.dig_stl = 0x3,
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.dig_thr = 1,
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.dig_thr_mode = 1,
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.dig_2ndo_sdm_mode = 0,
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.dig_hs_rate = 0, /* Not in TRM preferred settings */
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.dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
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.dll_trim_sel = 0x1,
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.dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
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.eq_lev = 0,
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.eq_ftc = 0x1f,
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.eq_ctl = 0,
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.eq_ovrd_lev = 1,
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.eq_ovrd_ftc = 1,
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},
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};
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static struct pipe3_data data_pcie = {
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.mode = PIPE3_MODE_PCIE,
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.settings = {
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/* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
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.ana_interface = INTERFACE_MODE_PCIE,
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.ana_losd = 0xa,
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.dig_fastlock = 1,
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.dig_lbw = 3,
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.dig_stepcnt = 0,
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.dig_stl = 0x3,
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.dig_thr = 1,
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.dig_thr_mode = 1,
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.dig_2ndo_sdm_mode = 0,
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.dig_hs_rate = 0,
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.dig_ovrd_hs_rate = 0,
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.dll_trim_sel = 0x2,
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.dll_phint_rate = 0x3,
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.eq_lev = 0,
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.eq_ftc = 0x1f,
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.eq_ctl = 1,
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.eq_ovrd_lev = 0,
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.eq_ovrd_ftc = 0,
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},
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};
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static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
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@ -324,32 +432,55 @@ static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
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static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
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{
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u32 val;
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struct pipe3_settings *s = &phy->settings;
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val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY);
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
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val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
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val |= (0x1 << INTERFACE_SHIFT | 0xA << LOSD_SHIFT);
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ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY, val);
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val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
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val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES);
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val &= ~(MEM_CDR_STEPCNT | MEM_CDR_STL_MASK | MEM_CDR_THR_MASK |
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MEM_CDR_CDR_2NDO_SDM_MODE | MEM_OVRD_HS_RATE);
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val |= (MEM_CDR_FASTLOCK | MEM_CDR_LBW | 0x3 << MEM_CDR_STL_SHIFT |
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0x1 << MEM_CDR_THR_SHIFT | MEM_CDR_THR_MODE);
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ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES, val);
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
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val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
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MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
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MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
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val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
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s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
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s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
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s->dig_lbw << MEM_CDR_LBW_SHIFT |
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s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
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s->dig_stl << MEM_CDR_STL_SHIFT |
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s->dig_thr << MEM_CDR_THR_SHIFT |
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s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
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s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
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val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_TRIM);
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val &= ~MEM_DLL_TRIM_SEL;
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val |= 0x2 << MEM_DLL_TRIM_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_TRIM, val);
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
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val &= ~MEM_DLL_TRIM_SEL_MASK;
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val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
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val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DLL);
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val |= MEM_DLL_PHINT_RATE;
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ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DLL, val);
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
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val &= ~MEM_DLL_PHINT_RATE_MASK;
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val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
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val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_EQUALIZER);
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val &= ~(MEM_EQLEV | MEM_EQCTL | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
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val |= MEM_EQFTC | 0x1 << MEM_EQCTL_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_EQUALIZER, val);
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val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
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val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
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MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
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val |= s->eq_lev << MEM_EQLEV_SHIFT |
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s->eq_ftc << MEM_EQFTC_SHIFT |
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s->eq_ctl << MEM_EQCTL_SHIFT |
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s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
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s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
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ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
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if (phy->mode == PIPE3_MODE_SATA) {
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val = ti_pipe3_readl(phy->phy_rx,
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SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
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val &= ~MEM_CDR_LOS_SOURCE_MASK;
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ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
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val);
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}
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}
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static int ti_pipe3_init(struct phy *x)
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@ -401,6 +532,8 @@ static int ti_pipe3_init(struct phy *x)
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return -EINVAL;
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}
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ti_pipe3_calibrate(phy);
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return ret;
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}
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@ -611,9 +744,6 @@ static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
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struct device *dev = phy->dev;
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struct platform_device *pdev = to_platform_device(dev);
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if (phy->mode != PIPE3_MODE_PCIE)
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return 0;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"phy_rx");
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phy->phy_rx = devm_ioremap_resource(dev, res);
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@ -669,6 +799,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
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phy->dev = dev;
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phy->mode = data->mode;
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phy->dpll_map = data->dpll_map;
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phy->settings = data->settings;
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ret = ti_pipe3_get_pll_base(phy);
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if (ret)
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