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spi: tegra114: switch to use modern name
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://msgid.link/r/20231128093031.3707034-12-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Yang Yingliang
Mark Brown
parent
8726bdcef6
commit
fe2e1c2225
1 changed files with 59 additions and 59 deletions
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@ -164,7 +164,7 @@ struct tegra_spi_client_data {
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struct tegra_spi_data {
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struct device *dev;
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struct spi_master *master;
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struct spi_controller *host;
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spinlock_t lock;
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struct clk *clk;
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@ -718,7 +718,7 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
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static int tegra_spi_set_hw_cs_timing(struct spi_device *spi)
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{
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struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
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struct spi_delay *setup = &spi->cs_setup;
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struct spi_delay *hold = &spi->cs_hold;
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struct spi_delay *inactive = &spi->cs_inactive;
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@ -772,7 +772,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
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bool is_first_of_msg,
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bool is_single_xfer)
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{
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struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
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struct tegra_spi_client_data *cdata = spi->controller_data;
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u32 speed = t->speed_hz;
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u8 bits_per_word = t->bits_per_word;
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@ -865,7 +865,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
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static int tegra_spi_start_transfer_one(struct spi_device *spi,
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struct spi_transfer *t, u32 command1)
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{
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struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
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unsigned total_fifo_words;
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int ret;
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@ -912,10 +912,10 @@ static struct tegra_spi_client_data
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*tegra_spi_parse_cdata_dt(struct spi_device *spi)
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{
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struct tegra_spi_client_data *cdata;
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struct device_node *slave_np;
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struct device_node *target_np;
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slave_np = spi->dev.of_node;
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if (!slave_np) {
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target_np = spi->dev.of_node;
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if (!target_np) {
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dev_dbg(&spi->dev, "device node not found\n");
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return NULL;
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}
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@ -924,9 +924,9 @@ static struct tegra_spi_client_data
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if (!cdata)
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return NULL;
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of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
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of_property_read_u32(target_np, "nvidia,tx-clk-tap-delay",
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&cdata->tx_clk_tap_delay);
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of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
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of_property_read_u32(target_np, "nvidia,rx-clk-tap-delay",
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&cdata->rx_clk_tap_delay);
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return cdata;
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}
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@ -942,7 +942,7 @@ static void tegra_spi_cleanup(struct spi_device *spi)
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static int tegra_spi_setup(struct spi_device *spi)
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{
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struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
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struct tegra_spi_client_data *cdata = spi->controller_data;
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u32 val;
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unsigned long flags;
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@ -993,7 +993,7 @@ static int tegra_spi_setup(struct spi_device *spi)
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static void tegra_spi_transfer_end(struct spi_device *spi)
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{
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struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
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int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
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/* GPIO based chip select control */
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@ -1025,11 +1025,11 @@ static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
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tegra_spi_readl(tspi, SPI_FIFO_STATUS));
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}
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static int tegra_spi_transfer_one_message(struct spi_master *master,
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static int tegra_spi_transfer_one_message(struct spi_controller *host,
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struct spi_message *msg)
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{
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bool is_first_msg = true;
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struct tegra_spi_data *tspi = spi_master_get_devdata(master);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
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struct spi_transfer *xfer;
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struct spi_device *spi = msg->spi;
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int ret;
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@ -1078,7 +1078,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
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reset_control_assert(tspi->rst);
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udelay(2);
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reset_control_deassert(tspi->rst);
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tspi->last_used_cs = master->num_chipselect + 1;
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tspi->last_used_cs = host->num_chipselect + 1;
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goto complete_xfer;
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}
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@ -1112,7 +1112,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
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ret = 0;
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exit:
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msg->status = ret;
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spi_finalize_current_message(master);
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spi_finalize_current_message(host);
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return ret;
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}
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@ -1293,40 +1293,40 @@ MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
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static int tegra_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct spi_controller *host;
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struct tegra_spi_data *tspi;
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struct resource *r;
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int ret, spi_irq;
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int bus_num;
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master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
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if (!master) {
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dev_err(&pdev->dev, "master allocation failed\n");
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host = spi_alloc_host(&pdev->dev, sizeof(*tspi));
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if (!host) {
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dev_err(&pdev->dev, "host allocation failed\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, master);
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tspi = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, host);
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tspi = spi_controller_get_devdata(host);
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if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
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&master->max_speed_hz))
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master->max_speed_hz = 25000000; /* 25MHz */
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&host->max_speed_hz))
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host->max_speed_hz = 25000000; /* 25MHz */
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/* the spi->mode bits understood by this driver: */
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master->use_gpio_descriptors = true;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
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SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
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master->setup = tegra_spi_setup;
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master->cleanup = tegra_spi_cleanup;
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master->transfer_one_message = tegra_spi_transfer_one_message;
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master->set_cs_timing = tegra_spi_set_hw_cs_timing;
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master->num_chipselect = MAX_CHIP_SELECT;
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master->auto_runtime_pm = true;
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host->use_gpio_descriptors = true;
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host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
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SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
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host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
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host->setup = tegra_spi_setup;
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host->cleanup = tegra_spi_cleanup;
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host->transfer_one_message = tegra_spi_transfer_one_message;
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host->set_cs_timing = tegra_spi_set_hw_cs_timing;
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host->num_chipselect = MAX_CHIP_SELECT;
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host->auto_runtime_pm = true;
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bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
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if (bus_num >= 0)
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master->bus_num = bus_num;
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host->bus_num = bus_num;
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tspi->master = master;
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tspi->host = host;
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tspi->dev = &pdev->dev;
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spin_lock_init(&tspi->lock);
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@ -1334,20 +1334,20 @@ static int tegra_spi_probe(struct platform_device *pdev)
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if (!tspi->soc_data) {
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dev_err(&pdev->dev, "unsupported tegra\n");
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ret = -ENODEV;
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goto exit_free_master;
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goto exit_free_host;
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}
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tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
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if (IS_ERR(tspi->base)) {
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ret = PTR_ERR(tspi->base);
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goto exit_free_master;
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goto exit_free_host;
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}
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tspi->phys = r->start;
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spi_irq = platform_get_irq(pdev, 0);
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if (spi_irq < 0) {
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ret = spi_irq;
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goto exit_free_master;
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goto exit_free_host;
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}
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tspi->irq = spi_irq;
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@ -1355,14 +1355,14 @@ static int tegra_spi_probe(struct platform_device *pdev)
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if (IS_ERR(tspi->clk)) {
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dev_err(&pdev->dev, "can not get clock\n");
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ret = PTR_ERR(tspi->clk);
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goto exit_free_master;
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goto exit_free_host;
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}
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tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
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if (IS_ERR(tspi->rst)) {
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dev_err(&pdev->dev, "can not get reset\n");
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ret = PTR_ERR(tspi->rst);
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goto exit_free_master;
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goto exit_free_host;
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}
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tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
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@ -1370,7 +1370,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
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ret = tegra_spi_init_dma_param(tspi, true);
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if (ret < 0)
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goto exit_free_master;
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goto exit_free_host;
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ret = tegra_spi_init_dma_param(tspi, false);
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if (ret < 0)
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goto exit_rx_dma_free;
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@ -1401,7 +1401,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
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tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
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tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
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tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
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tspi->last_used_cs = master->num_chipselect + 1;
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tspi->last_used_cs = host->num_chipselect + 1;
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pm_runtime_put(&pdev->dev);
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ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
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tegra_spi_isr_thread, IRQF_ONESHOT,
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@ -1412,10 +1412,10 @@ static int tegra_spi_probe(struct platform_device *pdev)
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goto exit_pm_disable;
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}
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master->dev.of_node = pdev->dev.of_node;
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ret = devm_spi_register_master(&pdev->dev, master);
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host->dev.of_node = pdev->dev.of_node;
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ret = devm_spi_register_controller(&pdev->dev, host);
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if (ret < 0) {
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dev_err(&pdev->dev, "can not register to master err %d\n", ret);
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dev_err(&pdev->dev, "can not register to host err %d\n", ret);
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goto exit_free_irq;
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}
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return ret;
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@ -1429,15 +1429,15 @@ static int tegra_spi_probe(struct platform_device *pdev)
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tegra_spi_deinit_dma_param(tspi, false);
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exit_rx_dma_free:
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tegra_spi_deinit_dma_param(tspi, true);
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exit_free_master:
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spi_master_put(master);
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exit_free_host:
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spi_controller_put(host);
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return ret;
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}
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static void tegra_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct tegra_spi_data *tspi = spi_master_get_devdata(master);
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struct spi_controller *host = platform_get_drvdata(pdev);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
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free_irq(tspi->irq, tspi);
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@ -1455,15 +1455,15 @@ static void tegra_spi_remove(struct platform_device *pdev)
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#ifdef CONFIG_PM_SLEEP
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static int tegra_spi_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct spi_controller *host = dev_get_drvdata(dev);
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return spi_master_suspend(master);
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return spi_controller_suspend(host);
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}
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static int tegra_spi_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_master_get_devdata(master);
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struct spi_controller *host = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
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int ret;
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ret = pm_runtime_resume_and_get(dev);
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@ -1473,17 +1473,17 @@ static int tegra_spi_resume(struct device *dev)
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}
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tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
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tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
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tspi->last_used_cs = master->num_chipselect + 1;
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tspi->last_used_cs = host->num_chipselect + 1;
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pm_runtime_put(dev);
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return spi_master_resume(master);
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return spi_controller_resume(host);
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}
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#endif
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static int tegra_spi_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_master_get_devdata(master);
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struct spi_controller *host = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
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/* Flush all write which are in PPSB queue by reading back */
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tegra_spi_readl(tspi, SPI_COMMAND1);
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@ -1494,8 +1494,8 @@ static int tegra_spi_runtime_suspend(struct device *dev)
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static int tegra_spi_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_master_get_devdata(master);
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struct spi_controller *host = dev_get_drvdata(dev);
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struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
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int ret;
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ret = clk_prepare_enable(tspi->clk);
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