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clk: sunxi-ng: Fix div/mult settings for osc12M on A64
The mult/div for osc12M was previously backwards (giving a 48M rate for osc12M). Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -566,7 +566,7 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
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0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
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/* Fixed Factor clocks */
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static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);
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static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
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/* We hardcode the divider to 4 for now */
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static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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