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dw_dmac: introduce software emulation of LLP transfers
Some controllers have the reduced functionality where the LLP multi block transfers are not supported. This patch introduces a support of such controllers. In case of memory copy or scatter-gather lists it emulates LLP transfers via bunch of the regular single block ones. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
parent
a09820043c
commit
fed2574b3c
2 changed files with 101 additions and 4 deletions
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@ -232,10 +232,29 @@ static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
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/*----------------------------------------------------------------------*/
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/* Perform single block transfer */
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static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
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struct dw_desc *desc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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u32 ctllo;
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/* Software emulation of LLP mode relies on interrupts to continue
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* multi block transfer. */
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ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
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channel_writel(dwc, SAR, desc->lli.sar);
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channel_writel(dwc, DAR, desc->lli.dar);
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channel_writel(dwc, CTL_LO, ctllo);
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channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
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channel_set_bit(dw, CH_EN, dwc->mask);
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}
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/* Called with dwc->lock held and bh disabled */
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static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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unsigned long was_soft_llp;
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/* ASSERT: channel is idle */
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if (dma_readl(dw, CH_EN) & dwc->mask) {
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@ -247,6 +266,26 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
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return;
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}
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if (dwc->nollp) {
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was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
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&dwc->flags);
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if (was_soft_llp) {
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dev_err(chan2dev(&dwc->chan),
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"BUG: Attempted to start new LLP transfer "
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"inside ongoing one\n");
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return;
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}
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dwc_initialize(dwc);
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dwc->tx_list = &first->tx_list;
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dwc->tx_node_active = first->tx_list.next;
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dwc_do_single_block(dwc, first);
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return;
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}
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dwc_initialize(dwc);
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channel_writel(dwc, LLP, first->txd.phys);
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@ -558,8 +597,36 @@ static void dw_dma_tasklet(unsigned long data)
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dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
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else if (status_err & (1 << i))
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dwc_handle_error(dw, dwc);
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else if (status_xfer & (1 << i))
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else if (status_xfer & (1 << i)) {
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
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if (dwc->tx_node_active != dwc->tx_list) {
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struct dw_desc *desc =
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list_entry(dwc->tx_node_active,
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struct dw_desc,
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desc_node);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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/* move pointer to next descriptor */
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dwc->tx_node_active =
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dwc->tx_node_active->next;
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dwc_do_single_block(dwc, desc);
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spin_unlock_irqrestore(&dwc->lock, flags);
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continue;
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} else {
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/* we are done here */
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clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
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}
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}
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spin_unlock_irqrestore(&dwc->lock, flags);
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dwc_scan_descriptors(dw, dwc);
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}
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}
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/*
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@ -962,6 +1029,8 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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} else if (cmd == DMA_TERMINATE_ALL) {
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spin_lock_irqsave(&dwc->lock, flags);
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clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
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dwc_chan_disable(dw, dwc);
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dwc->paused = false;
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@ -1204,6 +1273,13 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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if (dwc->nollp) {
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spin_unlock_irqrestore(&dwc->lock, flags);
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dev_dbg(chan2dev(&dwc->chan),
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"channel doesn't support LLP transfers\n");
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return ERR_PTR(-EINVAL);
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}
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if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
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spin_unlock_irqrestore(&dwc->lock, flags);
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dev_dbg(chan2dev(&dwc->chan),
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@ -1471,6 +1547,7 @@ static int __devinit dw_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&dw->dma.channels);
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for (i = 0; i < nr_channels; i++) {
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struct dw_dma_chan *dwc = &dw->chan[i];
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int r = nr_channels - i - 1;
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dwc->chan.device = &dw->dma;
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dma_cookie_init(&dwc->chan);
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@ -1482,7 +1559,7 @@ static int __devinit dw_probe(struct platform_device *pdev)
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/* 7 is highest priority & 0 is lowest. */
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if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
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dwc->priority = nr_channels - i - 1;
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dwc->priority = r;
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else
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dwc->priority = i;
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@ -1499,14 +1576,28 @@ static int __devinit dw_probe(struct platform_device *pdev)
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dwc->dw = dw;
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/* hardware configuration */
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if (autocfg)
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if (autocfg) {
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unsigned int dwc_params;
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dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
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DWC_PARAMS);
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/* Decode maximum block size for given channel. The
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* stored 4 bit value represents blocks from 0x00 for 3
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* up to 0x0a for 4095. */
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dwc->block_size =
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(4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
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else
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dwc->nollp =
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(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
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} else {
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dwc->block_size = pdata->block_size;
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/* Check if channel supports multi block transfer */
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channel_writel(dwc, LLP, 0xfffffffc);
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dwc->nollp =
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(channel_readl(dwc, LLP) & 0xfffffffc) == 0;
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channel_writel(dwc, LLP, 0);
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}
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}
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/* Clear all interrupts on all channels. */
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@ -172,6 +172,7 @@ struct dw_dma_regs {
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enum dw_dmac_flags {
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DW_DMA_IS_CYCLIC = 0,
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DW_DMA_IS_SOFT_LLP = 1,
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};
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struct dw_dma_chan {
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@ -182,6 +183,10 @@ struct dw_dma_chan {
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bool paused;
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bool initialized;
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/* software emulation of the LLP transfers */
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struct list_head *tx_list;
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struct list_head *tx_node_active;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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@ -195,6 +200,7 @@ struct dw_dma_chan {
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/* hardware configuration */
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unsigned int block_size;
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bool nollp;
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/* configuration passed via DMA_SLAVE_CONFIG */
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struct dma_slave_config dma_sconfig;
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