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drm/radeon: add get_allowed_info_register for EG/BTC
Registers that can be fetched from the info ioctl. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c6d2ac2c36
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ff609975e1
4 changed files with 34 additions and 0 deletions
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@ -1006,6 +1006,34 @@ static void evergreen_init_golden_registers(struct radeon_device *rdev)
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}
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}
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}
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}
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/**
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* evergreen_get_allowed_info_register - fetch the register for the info ioctl
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*
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* @rdev: radeon_device pointer
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* @reg: register offset in bytes
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* @val: register value
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*
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* Returns 0 for success or -EINVAL for an invalid register
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*
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*/
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int evergreen_get_allowed_info_register(struct radeon_device *rdev,
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u32 reg, u32 *val)
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{
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switch (reg) {
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case GRBM_STATUS:
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case GRBM_STATUS_SE0:
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case GRBM_STATUS_SE1:
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case SRBM_STATUS:
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case SRBM_STATUS2:
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case DMA_STATUS_REG:
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case UVD_STATUS:
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*val = RREG32(reg);
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return 0;
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default:
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return -EINVAL;
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}
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}
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void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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unsigned *bankh, unsigned *mtaspect,
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unsigned *bankh, unsigned *mtaspect,
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unsigned *tile_split)
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unsigned *tile_split)
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@ -1520,6 +1520,7 @@
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#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
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#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
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#define UVD_RBC_RB_RPTR 0xf690
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#define UVD_RBC_RB_RPTR 0xf690
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#define UVD_RBC_RB_WPTR 0xf694
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#define UVD_RBC_RB_WPTR 0xf694
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#define UVD_STATUS 0xf6bc
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/*
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/*
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* PM4
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* PM4
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@ -1344,6 +1344,7 @@ static struct radeon_asic evergreen_asic = {
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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.get_xclk = &rv770_get_xclk,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_allowed_info_register = evergreen_get_allowed_info_register,
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.gart = {
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.gart = {
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.get_page_entry = &rs600_gart_get_page_entry,
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.get_page_entry = &rs600_gart_get_page_entry,
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@ -1437,6 +1438,7 @@ static struct radeon_asic sumo_asic = {
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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.get_xclk = &r600_get_xclk,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_allowed_info_register = evergreen_get_allowed_info_register,
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.gart = {
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.gart = {
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.get_page_entry = &rs600_gart_get_page_entry,
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.get_page_entry = &rs600_gart_get_page_entry,
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@ -1529,6 +1531,7 @@ static struct radeon_asic btc_asic = {
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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.get_xclk = &rv770_get_xclk,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
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.get_allowed_info_register = evergreen_get_allowed_info_register,
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.gart = {
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.gart = {
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.tlb_flush = &evergreen_pcie_gart_tlb_flush,
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.get_page_entry = &rs600_gart_get_page_entry,
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.get_page_entry = &rs600_gart_get_page_entry,
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@ -548,6 +548,8 @@ struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
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unsigned num_gpu_pages,
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unsigned num_gpu_pages,
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struct reservation_object *resv);
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struct reservation_object *resv);
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int evergreen_get_temp(struct radeon_device *rdev);
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int evergreen_get_temp(struct radeon_device *rdev);
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int evergreen_get_allowed_info_register(struct radeon_device *rdev,
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u32 reg, u32 *val);
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int sumo_get_temp(struct radeon_device *rdev);
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int sumo_get_temp(struct radeon_device *rdev);
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int tn_get_temp(struct radeon_device *rdev);
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int tn_get_temp(struct radeon_device *rdev);
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int cypress_dpm_init(struct radeon_device *rdev);
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int cypress_dpm_init(struct radeon_device *rdev);
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