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net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
Sync initialization and calibration routines with MediaTek's reference
driver. Improves compliance and resolves link stability issues with
CH340 IoT devices connected to MT798x built-in PHYs.
Fixes: 98c485eaf5 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle
Jakub Kicinski
parent
cae1f1c366
commit
ff63cc2e95
1 changed files with 81 additions and 66 deletions
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@ -489,7 +489,7 @@ static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
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u16 reg, val;
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if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
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bias = -2;
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bias = -1;
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val = clamp_val(bias + tx_r50_cal_val, 0, 63);
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@ -705,6 +705,11 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
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static void mt798x_phy_common_finetune(struct phy_device *phydev)
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{
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
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__phy_write(phydev, 0x11, 0xc71);
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__phy_write(phydev, 0x12, 0xc);
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__phy_write(phydev, 0x10, 0x8fae);
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/* EnabRandUpdTrig = 1 */
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__phy_write(phydev, 0x11, 0x2f00);
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__phy_write(phydev, 0x12, 0xe);
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@ -715,15 +720,56 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x83aa);
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/* TrFreeze = 0 */
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/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
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__phy_write(phydev, 0x11, 0x240);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9680);
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/* TrFreeze = 0 (mt7988 default) */
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__phy_write(phydev, 0x11, 0x0);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9686);
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/* SSTrKp100 = 5 */
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/* SSTrKf100 = 6 */
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/* SSTrKp1000Mas = 5 */
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/* SSTrKf1000Mas = 6 */
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/* SSTrKp1000Slv = 5 */
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/* SSTrKf1000Slv = 6 */
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__phy_write(phydev, 0x11, 0xbaef);
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__phy_write(phydev, 0x12, 0x2e);
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__phy_write(phydev, 0x10, 0x968c);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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static void mt7981_phy_finetune(struct phy_device *phydev)
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{
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u16 val[8] = { 0x01ce, 0x01c1,
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0x020f, 0x0202,
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0x03d0, 0x03c0,
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0x0013, 0x0005 };
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int i, k;
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/* 100M eye finetune:
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* Keep middle level of TX MLT3 shapper as default.
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* Only change TX MLT3 overshoot level here.
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*/
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for (k = 0, i = 1; i < 12; i++) {
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if (i % 3 == 0)
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continue;
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phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
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}
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* ResetSyncOffset = 6 */
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__phy_write(phydev, 0x11, 0x600);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x8fc0);
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/* VgaDecRate = 1 */
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__phy_write(phydev, 0x11, 0x4c2a);
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__phy_write(phydev, 0x12, 0x3e);
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__phy_write(phydev, 0x10, 0x8fa4);
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/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
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* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
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@ -738,7 +784,7 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
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__phy_write(phydev, 0x10, 0x8ec0);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
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/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
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MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
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BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
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@ -771,48 +817,6 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
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phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
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}
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static void mt7981_phy_finetune(struct phy_device *phydev)
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{
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u16 val[8] = { 0x01ce, 0x01c1,
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0x020f, 0x0202,
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0x03d0, 0x03c0,
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0x0013, 0x0005 };
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int i, k;
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/* 100M eye finetune:
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* Keep middle level of TX MLT3 shapper as default.
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* Only change TX MLT3 overshoot level here.
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*/
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for (k = 0, i = 1; i < 12; i++) {
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if (i % 3 == 0)
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continue;
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phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
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}
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
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__phy_write(phydev, 0x11, 0xc71);
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__phy_write(phydev, 0x12, 0xc);
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__phy_write(phydev, 0x10, 0x8fae);
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/* ResetSyncOffset = 6 */
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__phy_write(phydev, 0x11, 0x600);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x8fc0);
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/* VgaDecRate = 1 */
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__phy_write(phydev, 0x11, 0x4c2a);
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__phy_write(phydev, 0x12, 0x3e);
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__phy_write(phydev, 0x10, 0x8fa4);
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/* FfeUpdGainForce = 4 */
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__phy_write(phydev, 0x11, 0x240);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9680);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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static void mt7988_phy_finetune(struct phy_device *phydev)
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{
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u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
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@ -827,17 +831,7 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
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/* TCT finetune */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
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/* Disable TX power saving */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
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MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
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__phy_write(phydev, 0x11, 0x671);
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__phy_write(phydev, 0x12, 0xc);
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__phy_write(phydev, 0x10, 0x8fae);
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/* ResetSyncOffset = 5 */
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__phy_write(phydev, 0x11, 0x500);
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__phy_write(phydev, 0x12, 0x0);
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@ -845,13 +839,27 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
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/* VgaDecRate is 1 at default on mt7988 */
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/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
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* MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
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*/
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__phy_write(phydev, 0x11, 0xb90a);
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__phy_write(phydev, 0x12, 0x6f);
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__phy_write(phydev, 0x10, 0x8f82);
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/* RemAckCntLimitCtrl = 1 */
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__phy_write(phydev, 0x11, 0xfbba);
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__phy_write(phydev, 0x12, 0xc3);
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__phy_write(phydev, 0x10, 0x87f8);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
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/* TxClkOffset = 2 */
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__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
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FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
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MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
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BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
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/* rg_tr_lpf_cnt_val = 1023 */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
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}
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static void mt798x_phy_eee(struct phy_device *phydev)
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@ -884,11 +892,11 @@ static void mt798x_phy_eee(struct phy_device *phydev)
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MTK_PHY_LPI_SLV_SEND_TX_EN,
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FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
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MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
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MTK_PHY_LPI_TXPCS_LOC_RCV,
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FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
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/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
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MTK_PHY_LPI_TXPCS_LOC_RCV);
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/* This also fixes some IoT issues, such as CH340 */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
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MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
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FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
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@ -922,7 +930,7 @@ static void mt798x_phy_eee(struct phy_device *phydev)
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9690);
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/* REG_EEE_st2TrKf1000 = 3 */
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/* REG_EEE_st2TrKf1000 = 2 */
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__phy_write(phydev, 0x11, 0x114f);
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__phy_write(phydev, 0x12, 0x2);
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__phy_write(phydev, 0x10, 0x969a);
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@ -947,7 +955,7 @@ static void mt798x_phy_eee(struct phy_device *phydev)
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96b8);
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/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
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/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
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__phy_write(phydev, 0x11, 0x1463);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96ca);
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@ -1459,6 +1467,13 @@ static int mt7988_phy_probe(struct phy_device *phydev)
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if (err)
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return err;
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/* Disable TX power saving at probing to:
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* 1. Meet common mode compliance test criteria
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* 2. Make sure that TX-VCM calibration works fine
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*/
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
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MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
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return mt798x_phy_calibration(phydev);
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}
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