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clk: imx: Add SCCG PLL type
The SCCG is a new PLL type introduced on i.MX8. The description of this SCCG clock can be found here: https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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6209624b9a
commit
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3 changed files with 267 additions and 1 deletions
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@ -13,7 +13,8 @@ obj-y += \
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clk-pllv1.o \
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clk-pllv2.o \
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clk-pllv3.o \
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clk-pfd.o
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clk-pfd.o \
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clk-sccg-pll.o
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obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
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obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
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256
drivers/clk/imx/clk-sccg-pll.c
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256
drivers/clk/imx/clk-sccg-pll.c
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@ -0,0 +1,256 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2018 NXP.
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*
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* This driver supports the SCCG plls found in the imx8m SOCs
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*
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* Documentation for this SCCG pll can be found at:
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* https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include <linux/bitfield.h>
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#include "clk.h"
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/* PLL CFGs */
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#define PLL_CFG0 0x0
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#define PLL_CFG1 0x4
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#define PLL_CFG2 0x8
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#define PLL_DIVF1_MASK GENMASK(18, 13)
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#define PLL_DIVF2_MASK GENMASK(12, 7)
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#define PLL_DIVR1_MASK GENMASK(27, 25)
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#define PLL_DIVR2_MASK GENMASK(24, 19)
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#define PLL_REF_MASK GENMASK(2, 0)
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#define PLL_LOCK_MASK BIT(31)
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#define PLL_PD_MASK BIT(7)
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#define OSC_25M 25000000
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#define OSC_27M 27000000
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#define PLL_SCCG_LOCK_TIMEOUT 70
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struct clk_sccg_pll {
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struct clk_hw hw;
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void __iomem *base;
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};
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#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw)
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static int clk_pll_wait_lock(struct clk_sccg_pll *pll)
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{
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u32 val;
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return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, 0,
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PLL_SCCG_LOCK_TIMEOUT);
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}
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static int clk_pll1_is_prepared(struct clk_hw *hw)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val;
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val = readl_relaxed(pll->base + PLL_CFG0);
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return (val & PLL_PD_MASK) ? 0 : 1;
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}
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static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val, divf;
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val = readl_relaxed(pll->base + PLL_CFG2);
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divf = FIELD_GET(PLL_DIVF1_MASK, val);
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return parent_rate * 2 * (divf + 1);
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}
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static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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u32 div;
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if (!parent_rate)
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return 0;
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div = rate / (parent_rate * 2);
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return parent_rate * div * 2;
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}
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static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val;
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u32 divf;
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if (!parent_rate)
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return -EINVAL;
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divf = rate / (parent_rate * 2);
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val = readl_relaxed(pll->base + PLL_CFG2);
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val &= ~PLL_DIVF1_MASK;
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val |= FIELD_PREP(PLL_DIVF1_MASK, divf - 1);
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writel_relaxed(val, pll->base + PLL_CFG2);
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return clk_pll_wait_lock(pll);
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}
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static int clk_pll1_prepare(struct clk_hw *hw)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val;
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val = readl_relaxed(pll->base + PLL_CFG0);
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val &= ~PLL_PD_MASK;
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writel_relaxed(val, pll->base + PLL_CFG0);
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return clk_pll_wait_lock(pll);
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}
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static void clk_pll1_unprepare(struct clk_hw *hw)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val;
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val = readl_relaxed(pll->base + PLL_CFG0);
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val |= PLL_PD_MASK;
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writel_relaxed(val, pll->base + PLL_CFG0);
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}
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static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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u32 val, ref, divr1, divf1, divr2, divf2;
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u64 temp64;
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val = readl_relaxed(pll->base + PLL_CFG0);
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switch (FIELD_GET(PLL_REF_MASK, val)) {
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case 0:
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ref = OSC_25M;
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break;
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case 1:
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ref = OSC_27M;
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break;
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default:
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ref = OSC_25M;
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break;
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}
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val = readl_relaxed(pll->base + PLL_CFG2);
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divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
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divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
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divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
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divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
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temp64 = ref * 2;
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temp64 *= (divf1 + 1) * (divf2 + 1);
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do_div(temp64, (divr1 + 1) * (divr2 + 1));
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return temp64;
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}
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static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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u32 div;
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unsigned long parent_rate = *prate;
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if (!parent_rate)
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return 0;
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div = rate / parent_rate;
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return parent_rate * div;
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}
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static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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u32 val;
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u32 divf;
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struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
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if (!parent_rate)
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return -EINVAL;
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divf = rate / parent_rate;
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val = readl_relaxed(pll->base + PLL_CFG2);
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val &= ~PLL_DIVF2_MASK;
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val |= FIELD_PREP(PLL_DIVF2_MASK, divf - 1);
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writel_relaxed(val, pll->base + PLL_CFG2);
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return clk_pll_wait_lock(pll);
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}
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static const struct clk_ops clk_sccg_pll1_ops = {
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.is_prepared = clk_pll1_is_prepared,
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.recalc_rate = clk_pll1_recalc_rate,
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.round_rate = clk_pll1_round_rate,
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.set_rate = clk_pll1_set_rate,
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};
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static const struct clk_ops clk_sccg_pll2_ops = {
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.prepare = clk_pll1_prepare,
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.unprepare = clk_pll1_unprepare,
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.recalc_rate = clk_pll2_recalc_rate,
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.round_rate = clk_pll2_round_rate,
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.set_rate = clk_pll2_set_rate,
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};
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struct clk *imx_clk_sccg_pll(const char *name,
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const char *parent_name,
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void __iomem *base,
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enum imx_sccg_pll_type pll_type)
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{
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struct clk_sccg_pll *pll;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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switch (pll_type) {
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case SCCG_PLL1:
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init.ops = &clk_sccg_pll1_ops;
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break;
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case SCCG_PLL2:
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init.ops = &clk_sccg_pll2_ops;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll->base = base;
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pll->hw.init = &init;
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return hw->clk;
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}
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@ -21,6 +21,11 @@ enum imx_pllv1_type {
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IMX_PLLV1_IMX35,
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};
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enum imx_sccg_pll_type {
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SCCG_PLL1,
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SCCG_PLL2,
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};
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struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
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const char *parent, void __iomem *base);
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struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
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void __iomem *base);
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struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
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void __iomem *base,
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enum imx_sccg_pll_type pll_type);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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