media: i2c: imx290: Add support for 74.25MHz external clock
The sensor supports either a 37.125 or 74.25MHz external, but the driver only supported 37.125MHz. Add the relevant register configuration for either clock frequency option. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Dave Stevenson
Mauro Carvalho Chehab
parent
044c2bfd00
commit
ffbe3d8251
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@ -105,6 +105,7 @@
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#define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452)
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#define IMX290_TLPX IMX290_REG_16BIT(0x3454)
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#define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472)
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#define IMX290_INCKSEL7 IMX290_REG_8BIT(0x3480)
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#define IMX290_PGCTRL_REGEN BIT(0)
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#define IMX290_PGCTRL_THRU BIT(1)
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@ -181,11 +182,29 @@ struct imx290_model_info {
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enum imx290_colour_variant colour_variant;
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};
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enum imx290_clk_freq {
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IMX290_CLK_37_125,
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IMX290_CLK_74_25,
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IMX290_NUM_CLK
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};
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struct imx290_regval {
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u32 reg;
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u32 val;
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};
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/*
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* Clock configuration for registers INCKSEL1 to INCKSEL6.
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*/
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struct imx290_clk_cfg {
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u8 incksel1;
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u8 incksel2;
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u8 incksel3;
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u8 incksel4;
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u8 incksel5;
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u8 incksel6;
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};
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struct imx290_mode {
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u32 width;
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u32 height;
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@ -195,6 +214,8 @@ struct imx290_mode {
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const struct imx290_regval *data;
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u32 data_size;
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const struct imx290_clk_cfg *clk_cfg;
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};
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struct imx290_csi_cfg {
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@ -213,6 +234,7 @@ struct imx290 {
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struct device *dev;
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struct clk *xclk;
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struct regmap *regmap;
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enum imx290_clk_freq xclk_idx;
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u8 nlanes;
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const struct imx290_model_info *model;
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@ -241,7 +263,6 @@ static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
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*/
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static const struct imx290_regval imx290_global_init_settings[] = {
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{ IMX290_EXTCK_FREQ, 0x2520 },
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{ IMX290_WINWV_OB, 12 },
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{ IMX290_WINPH, 0 },
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{ IMX290_WINPV, 0 },
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@ -291,7 +312,18 @@ static const struct imx290_regval imx290_global_init_settings[] = {
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{ IMX290_REG_8BIT(0x33b0), 0x50 },
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{ IMX290_REG_8BIT(0x33b2), 0x1a },
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{ IMX290_REG_8BIT(0x33b3), 0x04 },
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{ IMX290_REG_8BIT(0x3480), 0x49 },
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};
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#define IMX290_NUM_CLK_REGS 2
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static const struct imx290_regval xclk_regs[][IMX290_NUM_CLK_REGS] = {
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[IMX290_CLK_37_125] = {
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{ IMX290_EXTCK_FREQ, (37125 * 256) / 1000 },
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{ IMX290_INCKSEL7, 0x49 },
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},
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[IMX290_CLK_74_25] = {
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{ IMX290_EXTCK_FREQ, (74250 * 256) / 1000 },
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{ IMX290_INCKSEL7, 0x92 },
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},
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};
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static const struct imx290_regval imx290_1080p_settings[] = {
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@ -301,12 +333,6 @@ static const struct imx290_regval imx290_1080p_settings[] = {
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{ IMX290_OPB_SIZE_V, 10 },
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{ IMX290_X_OUT_SIZE, 1920 },
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{ IMX290_Y_OUT_SIZE, 1080 },
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{ IMX290_INCKSEL1, 0x18 },
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{ IMX290_INCKSEL2, 0x03 },
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{ IMX290_INCKSEL3, 0x20 },
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{ IMX290_INCKSEL4, 0x01 },
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{ IMX290_INCKSEL5, 0x1a },
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{ IMX290_INCKSEL6, 0x1a },
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};
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static const struct imx290_regval imx290_720p_settings[] = {
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@ -316,12 +342,6 @@ static const struct imx290_regval imx290_720p_settings[] = {
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{ IMX290_OPB_SIZE_V, 4 },
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{ IMX290_X_OUT_SIZE, 1280 },
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{ IMX290_Y_OUT_SIZE, 720 },
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{ IMX290_INCKSEL1, 0x20 },
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{ IMX290_INCKSEL2, 0x00 },
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{ IMX290_INCKSEL3, 0x20 },
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{ IMX290_INCKSEL4, 0x01 },
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{ IMX290_INCKSEL5, 0x1a },
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{ IMX290_INCKSEL6, 0x1a },
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};
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static const struct imx290_regval imx290_10bit_settings[] = {
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@ -427,6 +447,48 @@ static inline int imx290_link_freqs_num(const struct imx290 *imx290)
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return ARRAY_SIZE(imx290_link_freq_4lanes);
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}
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static const struct imx290_clk_cfg imx290_1080p_clock_config[] = {
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[IMX290_CLK_37_125] = {
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/* 37.125MHz clock config */
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.incksel1 = 0x18,
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.incksel2 = 0x03,
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.incksel3 = 0x20,
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.incksel4 = 0x01,
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.incksel5 = 0x1a,
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.incksel6 = 0x1a,
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},
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[IMX290_CLK_74_25] = {
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/* 74.25MHz clock config */
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.incksel1 = 0x0c,
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.incksel2 = 0x03,
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.incksel3 = 0x10,
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.incksel4 = 0x01,
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.incksel5 = 0x1b,
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.incksel6 = 0x1b,
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},
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};
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static const struct imx290_clk_cfg imx290_720p_clock_config[] = {
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[IMX290_CLK_37_125] = {
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/* 37.125MHz clock config */
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.incksel1 = 0x20,
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.incksel2 = 0x00,
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.incksel3 = 0x20,
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.incksel4 = 0x01,
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.incksel5 = 0x1a,
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.incksel6 = 0x1a,
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},
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[IMX290_CLK_74_25] = {
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/* 74.25MHz clock config */
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.incksel1 = 0x10,
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.incksel2 = 0x00,
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.incksel3 = 0x10,
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.incksel4 = 0x01,
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.incksel5 = 0x1b,
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.incksel6 = 0x1b,
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},
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};
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/* Mode configs */
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static const struct imx290_mode imx290_modes_2lanes[] = {
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{
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@ -437,6 +499,7 @@ static const struct imx290_mode imx290_modes_2lanes[] = {
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.link_freq_index = FREQ_INDEX_1080P,
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.data = imx290_1080p_settings,
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.data_size = ARRAY_SIZE(imx290_1080p_settings),
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.clk_cfg = imx290_1080p_clock_config,
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},
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{
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.width = 1280,
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@ -446,6 +509,7 @@ static const struct imx290_mode imx290_modes_2lanes[] = {
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.link_freq_index = FREQ_INDEX_720P,
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.data = imx290_720p_settings,
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.data_size = ARRAY_SIZE(imx290_720p_settings),
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.clk_cfg = imx290_720p_clock_config,
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},
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};
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@ -458,6 +522,7 @@ static const struct imx290_mode imx290_modes_4lanes[] = {
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.link_freq_index = FREQ_INDEX_1080P,
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.data = imx290_1080p_settings,
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.data_size = ARRAY_SIZE(imx290_1080p_settings),
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.clk_cfg = imx290_1080p_clock_config,
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},
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{
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.width = 1280,
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@ -467,6 +532,7 @@ static const struct imx290_mode imx290_modes_4lanes[] = {
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.link_freq_index = FREQ_INDEX_720P,
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.data = imx290_720p_settings,
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.data_size = ARRAY_SIZE(imx290_720p_settings),
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.clk_cfg = imx290_720p_clock_config,
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},
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};
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@ -592,6 +658,26 @@ static int imx290_set_register_array(struct imx290 *imx290,
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return 0;
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}
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static int imx290_set_clock(struct imx290 *imx290)
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{
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const struct imx290_mode *mode = imx290->current_mode;
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enum imx290_clk_freq clk_idx = imx290->xclk_idx;
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const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx];
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int ret;
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ret = imx290_set_register_array(imx290, xclk_regs[clk_idx],
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IMX290_NUM_CLK_REGS);
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imx290_write(imx290, IMX290_INCKSEL1, clk_cfg->incksel1, &ret);
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imx290_write(imx290, IMX290_INCKSEL2, clk_cfg->incksel2, &ret);
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imx290_write(imx290, IMX290_INCKSEL3, clk_cfg->incksel3, &ret);
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imx290_write(imx290, IMX290_INCKSEL4, clk_cfg->incksel4, &ret);
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imx290_write(imx290, IMX290_INCKSEL5, clk_cfg->incksel5, &ret);
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imx290_write(imx290, IMX290_INCKSEL6, clk_cfg->incksel6, &ret);
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return ret;
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}
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static int imx290_set_data_lanes(struct imx290 *imx290)
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{
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int ret = 0;
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@ -896,6 +982,13 @@ static int imx290_start_streaming(struct imx290 *imx290,
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return ret;
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}
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/* Set clock parameters based on mode and xclk */
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ret = imx290_set_clock(imx290);
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if (ret < 0) {
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dev_err(imx290->dev, "Could not set clocks\n");
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return ret;
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}
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/* Set data lane count */
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ret = imx290_set_data_lanes(imx290);
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if (ret < 0) {
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@ -1295,8 +1388,15 @@ static int imx290_init_clk(struct imx290 *imx290)
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return ret;
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}
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/* external clock must be 37.125 MHz */
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if (xclk_freq != 37125000) {
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/* external clock must be 37.125 MHz or 74.25MHz */
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switch (xclk_freq) {
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case 37125000:
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imx290->xclk_idx = IMX290_CLK_37_125;
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break;
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case 74250000:
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imx290->xclk_idx = IMX290_CLK_74_25;
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break;
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default:
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dev_err(imx290->dev, "External clock frequency %u is not supported\n",
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xclk_freq);
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return -EINVAL;
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