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ARM: 6473/1: Small update to ux500 specific L2 cache code
This change updates the ux500 specific outer cache code to use the new *_relaxed() I/O accessors. Signed-off-by: Per Fransson <per.xx.fransson@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 3 additions and 3 deletions
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@ -75,14 +75,14 @@ void __init ux500_init_irq(void)
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static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* wait for the operation to complete */
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while (readl(reg) & mask)
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while (readl_relaxed(reg) & mask)
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;
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}
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static inline void ux500_cache_sync(void)
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{
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void __iomem *base = __io_address(UX500_L2CC_BASE);
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writel(0, base + L2X0_CACHE_SYNC);
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writel_relaxed(0, base + L2X0_CACHE_SYNC);
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ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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@ -107,7 +107,7 @@ static void ux500_l2x0_inv_all(void)
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uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
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/* invalidate all ways */
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writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
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ux500_cache_sync();
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}
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