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ARM: at91: pm: avoid soft resetting AC DLL
[ Upstream commitcef8cdc0d0
] Do not soft reset AC DLL as controller is buggy and this operation my introduce glitches in the controller leading to undefined behavior. Fixes:f0bbf17958
("ARM: at91: pm: add self-refresh support for sama7g5") Depends-on:a02875c4cb
("ARM: at91: pm: fix self-refresh for sama7g5") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221026124114.985876-2-claudiu.beznea@microchip.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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e183378ddd
commit
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2 changed files with 10 additions and 2 deletions
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@ -169,10 +169,15 @@ sr_ena_2:
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cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
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cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
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bne sr_ena_2
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bne sr_ena_2
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/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
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/* Disable DX DLLs for non-backup modes. */
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cmp r7, #AT91_PM_BACKUP
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cmp r7, #AT91_PM_BACKUP
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beq sr_ena_3
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beq sr_ena_3
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/* Do not soft reset the AC DLL. */
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ldr tmp1, [r3, DDR3PHY_ACDLLCR]
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bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
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str tmp1, [r3, DDR3PHY_ACDLLCR]
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/* Disable DX DLLs. */
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/* Disable DX DLLs. */
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ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
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ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
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orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
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orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
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@ -26,7 +26,10 @@
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#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
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#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
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#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
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#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
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#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
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#define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
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#define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
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#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
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#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
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#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
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#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
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#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
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#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
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#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
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