This adds in the x3proto and magicpanelr2 mach types, plugs in
highlander and rts7751r2d groups, and also hooks up the r2d
subtypes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
R7780RP can't do byte-sized accesses to CF, so needs to do word
sized access with low-byte masking. This same problem exists
on older versions of the R2D, with the same workaround having
been implemented in 43f4b8c757
there. Follow that change for the highlander boards.
This does not impact R7780MP or SH7785 based Highlander modules.
If you're unfortunate enough to be stuck with an R7780RP, this
patch is for you!
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
It's assumed that .eh_frame is terminated with 4-byte 0 in shared
libraries and executable. It seems to be the case for VDSOs too.
Without this terminator, I saw failures when unwinding from VDSO,
though I don't know how other architectures handle this issue.
For the normal libs, crtendS.o gives this terminator. We can use
such terminating objects. Or we can add a 4-byte 0 with modifying
the linker script like as the patch below.
Signed-off-by: Kaz Kojima <kkojima@rr.iij4u.or.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
While using separate IRQ stacks can cut down on stack consumption,
many users can also use 4k stacks directly without the additional
need of separate stacks for soft and hardirqs.
With this split, we support the same rationale for 4KSTACKS as
m68knommu, with the IRQSTACKS abstraction as per ppc64.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
movca.l is restricted to SH-4 and up only, though compilers that
are unable to support ISA tuning (especially older versions of
binutils) will happily compile in the bogus opcode on older parts.
Conditionalize it to fix SH-3 regressions noted by Kristoffer.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CPU_HAS_SR_RB is selected by both CPU_SH3 and CPU_SH4, so having a
dependency and default y on those additionally doesn't make much sense.
The select also has to be special cased for CPUs that don't support
this.
This is also something that has been abused too much as a result
of being user-visible, hence the addition of the select in the first
place. So just kill the user-visibility entirely while we're at it.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Converts from the profile notifier to the timer hook. Follows
the generic timer interrupt-based change.
This really wants to be converted to perfmon..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Some cleanups to the SH linker script. This reorders some of the
data sections for more optimal placement, general tabification,
and plugging in omitted generic definitions.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
When the SH kernel used to support embedding a ramdisk in the
pre-initramfs days it was placed in a special section and made to
look like a regular initrd. Since that was removed ages ago, kill
off the remaining cruft that was missed.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
memory_end was being clobbered by whatever the kernel config had
specified, rather than obeying the setup option. Fix this up so
that memory_end is only initialized if nothing has been set on
the command line.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Starting with binutils somewhere around 2.17.50.14 the vmlinux file
contains a ".note.gnu.build-id" section which doesn't get removed when
the zImage is built; resulting in a 2GB intermediate file and a broken
zImage.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
I'm converting most array size calculations under arch/ to use the
ARRAY_SIZE() macro. This is the (tiny) patch for sh.
Signed-off-by: Alejandro Martinez Ruiz <alex@flawedcode.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Remove reference to out of date/rotting websites.
Signed-off-by: Adrian McMenamin <adrian@mcmen.demon.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for the ax88796 driver on highlander boards.
Implemented using the 93cx6 EEPROM support introduced by commit-id
89e536a190.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This reverts commit 2e1c49db4c.
First off, testing in Fedora has shown it to cause boot failures,
bisected down by Martin Ebourne, and reported by Dave Jobes. So the
commit will likely be reverted in the 2.6.23 stable kernels.
Secondly, in the 2.6.24 model, x86-64 has now grown support for
SPARSEMEM_VMEMMAP, which disables the relevant code anyway, so while the
bug is not visible any more, it's become invisible due to the code just
being irrelevant and no longer enabled on the only architecture that
this ever affected.
Reported-by: Dave Jones <davej@redhat.com>
Tested-by: Martin Ebourne <fedora@ebourne.me.uk>
Cc: Zou Nan hai <nanhai.zou@intel.com>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Acked-by: Andy Whitcroft <apw@shadowen.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().
As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.
This is where the following code in local_r4k_flush_cache_page() strikes:
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (cpu_context(smp_processor_id(), mm) == 0)
return;
On VSMP and SMTC had a function of cpu_context() for each CPU(TC).
So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.
While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().
Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.
This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Enable the onboard GenBus IDE interface in the default configuration.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache. Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.
While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A comment on ptrace_getregs() states "Registers are sign extended to
fill the available space." but it is not true. Fix code to match the
comment. Also fix casts on each caller to get rid of some warnings.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch separates the platform devices registration for the MTX-1
specific devices: GPIO leds and watchdog.
[Minor fixup and formatting change -- Ralf]
Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Mmap with MAP_FIXED was not validating the addr and len parameters. This
leads to the failure of GCC's gcc.c-torture/execute/loop-2[fg].c testcases
when using the o32 ABI on a 64 bit kernel.
These testcases try to mmap 65536 bytes at 0x7fff8000 and then access all
the memory. In 2.6.18 and 2.6.23.1 (and likely other versions as well)
the kernel maps the requested memory, but since half of it is above
0x80000000 a SIGBUS is generated when it is accessed.
This patch moves the len validation above the MAP_FIXED processing so that
it is always validated. It also adds validation to the addr parameter for
MAP_FIXED mappings.
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Try increasingly longer time periods starting of at 0x10 cycles. This
should be fast on hardware and work nicely with emulators.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The expression "(long)(read_c0_count() - cnt)" can never be a negative
value on 64-bit kernel. Cast to "int" before comparison.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
They break the timer interrupt initialization and only seem to be a kludge
for initialization happening in the wrong order. Further testing done by
Thiemo confirms the suspicion that the other invocations also seem to have
useless.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode. The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.
Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore. The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
to handle the alternate timer interrupt of the RM9000.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Since the cp0 compare interrupt handler isn't initialized by the time
plat_time_init is called don't set IE_IRQ5 anymore, cevt-r4k.c will do
that a little later itself.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The old plat_timer_setup hook is no longer getting called so the Alchemy
time initialization was getting skipped.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
clockevent_delta2ns() use the shift and mult value, so
clockevent_set_clock() should be called first.
Pointed out by Atsushi Nemoto.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
set_next_event() and set_mode() are always called with interrupt disabled.
irqsave and irqrestore are not necessary for spinlock.
Pointed out by Atsushi Nemoto.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
