Commit graph

6507 commits

Author SHA1 Message Date
Grygorii Strashko
69e3002837 clk: ti: dra7: fix parent for gmac_clkctrl
The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
Hence, fix it.

Fixes: dffa9051d5 ('clk: ti: dra7: add new clkctrl data')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-20 09:41:28 +02:00
Benoit Parrot
7dfd5e619d clk: ti: dra7: add vpe clkctrl data
Add clkctrl data for VPE.

Signed-off-by: Benoit Parrot <bparrot@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-20 09:39:52 +02:00
Benoit Parrot
7054c14f05 clk: ti: dra7: add cam clkctrl data
Add clkctrl data for CAM domain.

Signed-off-by: Benoit Parrot <bparrot@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-20 09:36:50 +02:00
Linus Torvalds
575966e080 ARM: SoC fixes
I've been sitting on these longer than I meant, so the patch count is
 a bit higher than ideal for this part of the release. There's also some
 reverts of double-applied patches that brings the diffstat up a bit.
 
 With that said, the biggest changes are:
 
  - Revert of duplicate i2c device addition on two Aspeed (BMC) Devicetrees.
  - Move of two device nodes that got applied to the wrong part of the
    tree on ASpeed G6.
  - Regulator fix for Beaglebone X15 (adding 12/5V supplies)
  - Use interrupts for keys on Amlogic SM1 to avoid missed polls
 
 In addition to that, there is a collection of smaller DT fixes:
 
  - Power supply assignment fixes for i.MX6
  - Fix of interrupt line for magnetometer on i.MX8 Librem5 devkit
  - Build fixlets (selects) for davinci/omap2+
  - More interrupt number fixes for Stratix10, Amlogic SM1, etc.
  - ... and more similar fixes across different platforms
 
 And some non-DT stuff:
 
  - optee fix to register multiple shared pages properly
  - Clock calculation fixes for MMP3
  - Clock fixes for OMAP as well
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "I've been sitting on these longer than I meant, so the patch count is
  a bit higher than ideal for this part of the release. There's also
  some reverts of double-applied patches that brings the diffstat up a
  bit.

  With that said, the biggest changes are:

   - Revert of duplicate i2c device addition on two Aspeed (BMC)
     Devicetrees.

   - Move of two device nodes that got applied to the wrong part of the
     tree on ASpeed G6.

   - Regulator fix for Beaglebone X15 (adding 12/5V supplies)

   - Use interrupts for keys on Amlogic SM1 to avoid missed polls

  In addition to that, there is a collection of smaller DT fixes:

   - Power supply assignment fixes for i.MX6

   - Fix of interrupt line for magnetometer on i.MX8 Librem5 devkit

   - Build fixlets (selects) for davinci/omap2+

   - More interrupt number fixes for Stratix10, Amlogic SM1, etc.

   - ... and more similar fixes across different platforms

  And some non-DT stuff:

   - optee fix to register multiple shared pages properly

   - Clock calculation fixes for MMP3

   - Clock fixes for OMAP as well"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits)
  MAINTAINERS: Add myself as the co-maintainer for Actions Semi platforms
  ARM: dts: imx7: Fix Toradex Colibri iMX7S 256MB NAND flash support
  ARM: dts: imx6sll-evk: Remove incorrect power supply assignment
  ARM: dts: imx6sl-evk: Remove incorrect power supply assignment
  ARM: dts: imx6sx-sdb: Remove incorrect power supply assignment
  ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment
  ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL
  ARM: omap2plus: select RESET_CONTROLLER
  ARM: davinci: select CONFIG_RESET_CONTROLLER
  ARM: dts: aspeed: rainier: Fix fan fault and presence
  ARM: dts: aspeed: rainier: Remove duplicate i2c busses
  ARM: dts: aspeed: tacoma: Remove duplicate flash nodes
  ARM: dts: aspeed: tacoma: Remove duplicate i2c busses
  ARM: dts: aspeed: tacoma: Fix fsi master node
  ARM: dts: aspeed-g6: Fix FSI master location
  ARM: dts: mmp3: Fix the TWSI ranges
  clk: mmp2: Fix the order of timer mux parents
  ARM: mmp: do not divide the clock rate
  arm64: dts: rockchip: Fix IR on Beelink A1
  optee: Fix multi page dynamic shm pool alloc
  ...
2020-01-16 19:42:08 -08:00
Stephen Boyd
a0af274247 Our usual set of fixes for Allwinner, to fix the number of reported
clocks on the v3s, fixing the external clock on the R40, and some
 fixes for the AR100 co-processor clocks.
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Merge tag 'sunxi-clk-fixes-for-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clk fixes from Maxime Ripard:

Our usual set of fixes for Allwinner, to fix the number of reported
clocks on the v3s, fixing the external clock on the R40, and some
fixes for the AR100 co-processor clocks.

* tag 'sunxi-clk-fixes-for-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order
  clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
  clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
  clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs
  clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
2020-01-13 09:55:41 -08:00
Anson Huang
9c140d9926 clk: imx: Add support for i.MX8MP clock driver
Add clock driver support for i.MX8MP which is a new SoC of i.MX8M
family.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12 14:07:36 +08:00
Anson Huang
83dea32c5c clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
Switch the imx_clk_gate4_flags() function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12 14:07:11 +08:00
Dmitry Osipenko
41a1f096e9 clk: tegra20/30: Explicitly set parent clock for Video Decoder
The VDE parent won't be changed automatically to PLLC if bootloader
didn't do that for us, hence let's explicitly set the parent for
consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10 15:50:43 +01:00
Dmitry Osipenko
cb98598e68 clk: tegra20/30: Don't pre-initialize displays parent clock
Both Tegra20 and Tegra30 are initializing display's parent clock
incorrectly because PLLP is running at 216/408MHz while display rate is
set to 600MHz, but pre-setting the parent isn't needed at all because
display driver selects proper parent anyways.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10 15:50:25 +01:00
Dmitry Osipenko
cf83a28f28 clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
UART clock is divided using divisor values from DLM/DLL registers when
enable-bit is unset in clk register and clk's divider configuration isn't
taken onto account in this case. This doesn't cause any problems, but
let's add a check for the divider's enable-bit state, for consistency.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10 15:50:05 +01:00
Sowjanya Komatineni
d8edf5280c clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
pm_runtime_irq_safe() is not needed as interrupts are allowed during
suspend and resume. This was added mistakenly during DFLL suspend and
resume support patch.

While at it, also update the description of the dev argument that is
passed to the tegra_dfll_suspend() function.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10 15:39:03 +01:00
Sricharan R
d9db07f088 clk: qcom: Add ipq6018 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq6018 based devices.

Also fixed the sparse warnings reported by,
Reported-by: kbuild test robot <lkp@intel.com>
Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Co-developed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Link: https://lkml.kernel.org/r/1578557121-423-3-git-send-email-sricharan@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-09 12:42:55 -08:00
Olof Johansson
40a9012a3b Initial support for hierarchical CPU arrangement, managed by PSCI and its
corresponding cpuidle driver. This support is based upon using the generic
 PM domain, which already supports devices belonging to CPUs.
 
 Finally, these is a DTS patch that enables the hierarchical topology to be
 used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated
 mode.
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Merge tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm into arm/drivers

Initial support for hierarchical CPU arrangement, managed by PSCI and its
corresponding cpuidle driver. This support is based upon using the generic
PM domain, which already supports devices belonging to CPUs.

Finally, these is a DTS patch that enables the hierarchical topology to be
used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated
mode.

* tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm: (611 commits)
  arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916
  cpuidle: psci: Add support for PM domains by using genpd
  PM / Domains: Introduce a genpd OF helper that removes a subdomain
  cpuidle: psci: Support CPU hotplug for the hierarchical model
  cpuidle: psci: Manage runtime PM in the idle path
  cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains
  cpuidle: psci: Attach CPU devices to their PM domains
  cpuidle: psci: Add a helper to attach a CPU to its PM domain
  cpuidle: psci: Support hierarchical CPU idle states
  cpuidle: psci: Simplify OF parsing of CPU idle state nodes
  cpuidle: dt: Support hierarchical CPU idle states
  of: base: Add of_get_cpu_state_node() to get idle states for a CPU node
  firmware: psci: Export functions to manage the OSI mode
  dt: psci: Update DT bindings to support hierarchical PSCI states
  cpuidle: psci: Align psci_power_state count with idle state count
  Linux 5.5-rc4
  locks: print unsigned ino in /proc/locks
  riscv: export flush_icache_all to modules
  riscv: reject invalid syscalls below -1
  riscv: fix compile failure with EXPORT_SYMBOL() & !MMU
  ...

Link: https://lore.kernel.org/r/20200102160820.3572-1-ulf.hansson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-08 10:26:29 -08:00
Stephen Warren
bf83b96f87 clk: tegra: Mark fuse clock as critical
For a little over a year, U-Boot on Tegra124 has configured the flow
controller to perform automatic RAM re-repair on off->on power
transitions of the CPU rail[1]. This is mandatory for correct operation
of Tegra124. However, RAM re-repair relies on certain clocks, which the
kernel must enable and leave running. The fuse clock is one of those
clocks. Mark this clock as critical so that LP1 power mode (system
suspend) operates correctly.

[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair

Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08 12:55:19 +01:00
Geert Uytterhoeven
8040bf4091 clk: renesas: Prepare for split of R-Car H3 config symbol
Despite using the same compatible values ("r8a7795"-based) because of
historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+
(R8A77951) are really different SoCs, with different part numbers.
Hence the SoC configuration symbol will be split in two separate config
symbols.

As the Clock Pulse Generator / Module Standby and Software Reset blocks
in both SoCs are very similar, they will keep on sharing a driver.
Extend the dependency of CONFIG_CLK_R8A7795, to prepare for the split.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20191230080902.2832-1-geert+renesas@glider.be
2020-01-08 09:52:43 +01:00
Stephen Boyd
ff25881713 clk: divider: Add support for specifying parents via DT/pointers
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a divider clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-13-sboyd@kernel.org
[sboyd@kernel.org: Export __clk_hw_register_divider]
2020-01-07 23:08:02 -08:00
Martin Blumenstingl
8daeaea99c clk: meson: meson8b: make the CCF use the glitch-free mali mux
The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.

This fixes a potential hang when changing the GPU frequency at runtime.

Fixes: 74e1f2521f ("clk: meson: meson8b: add the GPU clock tree")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-01-07 11:30:50 +01:00
Stephen Boyd
194efb6e26 clk: gate: Add support for specifying parents via DT/pointers
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a gate clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-12-sboyd@kernel.org
2020-01-06 23:10:12 -08:00
Stephen Boyd
9611b3aacc clk: mux: Add support for specifying parents via DT/pointers
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a mux clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.

Note: the msm drm driver passes an anonymous array through the macro
which seems to confuse my compiler. Adding a parenthesis around the
whole thing at the call site seems to fix it but it must be wrong. Maybe
it's better to split this patch and pick out the array bits there?

Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-11-sboyd@kernel.org
2020-01-06 23:10:05 -08:00
Stephen Boyd
728e309674 clk: asm9260: Use parent accuracy in fixed rate clk
This fixed rate clk is registered with the accuracy of the parent. Use
CLK_FIXED_RATE_PARENT_ACCURACY for that instead of getting the parent
clk and finding out the accuracy that way.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-10-sboyd@kernel.org
2020-01-06 23:08:16 -08:00
Stephen Boyd
58f0c4ba56 clk: fixed-rate: Add clk flags for parent accuracy
Some clk providers want to use the accuracy of the parent clk and use
the fixed rate basic type clk to do that. This requires getting the
parent clk and extracting the accuracy before registering the fixed rate
clk. Let's add a flag for this and update the clk_ops to support this.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-8-sboyd@kernel.org
2020-01-06 23:07:34 -08:00
Lubomir Rintel
be61795bbd clk: mmp2: Add HSIC clocks
There are two USB HSIC controllers on MMP2 and MMP3.

Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06 09:33:18 -08:00
Lubomir Rintel
8bea5ac0fb clk: mmp2: Fix the order of timer mux parents
Determined empirically, no documentation is available.

The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee43 ("ARM: mmp/mmp2: dt: enable the clock")'

Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06 09:19:07 -08:00
Bjorn Andersson
ab91f72e01 clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the
SoC. Update the definition of these clocks to allow this to be wired up
to the appropriate clock source.

Retain "xo" as the global named parent to make the change a nop in the
event that DT doesn't carry the necessary clocks definition.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06 08:55:28 -08:00
Taniya Das
bcd63d222b clk: qcom: rpmh: Add IPA clock for SC7180
The Qualcomm IP Accelerator (IPA) clock resource that is managed by the BCM is
required by the IPA driver in order to scale its core clock.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1578305923-29125-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06 08:54:16 -08:00
Taniya Das
924e2d0155 clk: qcom: rpmh: skip undefined clocks when registering
When iterating over a platform's available clocks in clk_rpmh_probe(),
check for undefined (null) entries in the clocks array.  Not all
clock indexes necessarily have clocks defined.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1578305923-29125-2-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Leave 'name' declaration at beginning of loop]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06 08:53:44 -08:00
Christoph Hellwig
4bdc0d676a remove ioremap_nocache and devm_ioremap_nocache
ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2020-01-06 09:45:59 +01:00
Geert Uytterhoeven
37215da555 clk: Add support for setting clk_rate via debugfs
For testing, it is useful to be able to specify a clock rate manually.
As this is a dangerous feature, it is not enabled by default.
Users need to modify the source directly and #define
CLOCK_ALLOW_WRITE_DEBUGFS.

This follows the spirit of commit 09c6ecd394 ("regmap: Add support
for writing to regmap registers via debugfs").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lkml.kernel.org/r/20190828132306.19012-1-geert+renesas@glider.be
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05 19:12:58 -08:00
Eugen Hristev
66d9f5214c clk: at91: sam9x60: fix programmable clock prescaler
The prescaler works as parent rate divided by (PRES + 1) (is_pres_direct == 1)
It does not work in the way of parent rate shifted to the right by (PRES + 1),
which means division by 2^(PRES + 1) (is_pres_direct == 0)
Thus is_pres_direct must be enabled for this SoC, to make the right computation.
This field was added in
commit 45b0668211 ("clk: at91: fix programmable clock for sama5d2")
SAM9X60 has the same field as SAMA5D2 in the PCK

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1575977088-16781-1-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05 19:06:54 -08:00
Eugen Hristev
db2f44820a clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
Product datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1573478913-19737-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05 19:06:31 -08:00
Peter Ujfalusi
ad931a2d56 clk: ti: dra7-atl: Remove pm_runtime_irq_safe()
This is not needed for anything, and prevents proper PM transitions for
parent devices which is bad in case of ti-sysc; this effectively kills
PM completely. Thus, remove the flag.

Suggested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lkml.kernel.org/r/20191114101718.20619-1-peter.ujfalusi@ti.com
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05 19:04:19 -08:00
Stephen Boyd
2d34f09e79 clk: fixed-rate: Add support for specifying parents via DT/pointers
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a fixed rate clk with
different parent information. Then add a bunch of wrapper macros that
only pass down what needs to be passed down to the generic function to
support this with less arguments.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-7-sboyd@kernel.org
2020-01-05 13:35:12 -08:00
Stephen Boyd
38d1e38093 clk: fixed-rate: Move to_clk_fixed_rate() to C file
The only user of this macro is the fixed rate basic type. Move it there
to avoid polluting provider drivers.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-5-sboyd@kernel.org
2020-01-05 13:34:37 -08:00
Stephen Boyd
576859dfc5 clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
There aren't any users of this API anymore. Remove it.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-4-sboyd@kernel.org
2020-01-05 13:34:37 -08:00
Stephen Boyd
34e018336f clk: fixed-rate: Convert to clk_hw based APIs
This code still uses struct clk to register clks from the probe path.
Migrate this to the clk_hw based APIs to modernize the code. Also, this
isn't a module and it can't be one because the driver is always builtin
so drop the module table.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-3-sboyd@kernel.org
2020-01-05 13:34:37 -08:00
Stephen Boyd
9a9b5a4af0 clk: gpio: Use DT way of specifying parents
Nobody has used the gpio clk registration functions nor the gpio clk_ops
exposed by the basic gpio clk type. Let's remove all those APIs and move
the gpio clk support into the C file. Since nothing is using the
exported APIs, simplify the driver to be a platform driver that uses
clk_parent_data to pick 0th or 1st cell of the node's clocks property.

Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-2-sboyd@kernel.org
2020-01-05 13:34:36 -08:00
Georgi Djakov
5e82548e26 clk: qcom: gcc-sdm845: Add missing flag to votable GDSCs
On sdm845 devices, during boot we see the following warnings (unless we
have added 'pd_ignore_unused' to the kernel command line):
	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on'
	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on'
	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on'
	hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on'
	hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on'
	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on'
	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on'

As the name of these GDSCs suggests, they are "votable" and in downstream
DT, they all have the property "qcom,no-status-check-on-disable", which
means that we should not poll the status bit when we disable them.

Luckily the VOTABLE flag already exists and it does exactly what we need,
so let's make use of it to make the warnings disappear.

Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.org
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05 12:02:21 -08:00
Krzysztof Kozlowski
333d2d19df clk: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
	$ sed -e 's/^        /\t/' -i */Kconfig

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lkml.kernel.org/r/1574306335-29026-1-git-send-email-krzk@kernel.org
[sboyd@kernel.org: Fixup mediatek to have two spaces for help indent]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:34:39 -08:00
Linus Walleij
248fdcc77a clk: ux500: Fix up the SGA clock for some variants
Some of the special PRCMU firmware variants were not
properly detected in the Ux500 clock driver, resulting
in the wrong clock for the SGA.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20191217210504.27888-1-linus.walleij@linaro.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:27:15 -08:00
Taniya Das
253dc75a0b clk: qcom: Add video clock controller driver for SC7180
Add support for the video clock controller found on SC7180
based devices. This would allow video drivers to probe
and control their clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1577428714-17766-7-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:25:01 -08:00
Taniya Das
745ff069a4 clk: qcom: Add graphics clock controller driver for SC7180
Add support for the graphics clock controller found on SC7180
based devices. This would allow graphics drivers to probe and
control their clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1577428714-17766-4-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:25:00 -08:00
Stephen Boyd
2d26999261 clk: Warn about critical clks that fail to enable
If we don't warn here users of the CLK_IS_CRITICAL flag may not know
that their clk isn't actually enabled because it silently fails to
enable. Let's print a warning in that case so developers find these
problems faster.

Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200102005503.71923-1-sboyd@kernel.org
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
2020-01-04 23:21:08 -08:00
Niklas Cassel
fbefb7cc8e clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
Allow accessing the parent clock names required for the driver operation
by using the device tree 'clock-names' property, while falling back to
the previous method of using names in the global name space.

This permits extending the driver to other platforms without having to
modify its source code.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Link: https://lkml.kernel.org/r/20200103111429.1347-1-nks@flawful.org
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:15:47 -08:00
Kunihiko Hayashi
1ec09a2ec6 clk: uniphier: Add SCSSI clock gate for each channel
SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee365 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04 23:14:22 -08:00
Stephen Boyd
e7ce74bc0e Merge branch 'clk-register-dt-node-better' into clk-qcom
* clk-register-dt-node-better:
  clk: Use parent node pointer during registration if necessary
2020-01-04 23:08:57 -08:00
Stephen Boyd
9011f92622 clk: Use parent node pointer during registration if necessary
Sometimes clk drivers are attached to devices which are children of a
parent device that is connected to a node in DT. This happens when
devices are MFD-ish and the parent device driver mostly registers child
devices to match against drivers placed in their respective subsystem
directories like drivers/clk, drivers/regulator, etc. When the clk
driver calls clk_register() with a device pointer, that struct device
pointer won't have a device_node associated with it because it was
created purely in software as a way to partition logic to a subsystem.

This causes problems for the way we find parent clks for the clks
registered by these child devices because we look at the registering
device's device_node pointer to lookup 'clocks' and 'clock-names'
properties. Let's use the parent device's device_node pointer if the
registering device doesn't have a device_node but the parent does. This
simplifies clk registration code by avoiding the need to assign some
device_node to the device registering the clk.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20191230190455.141339-1-sboyd@kernel.org
[sboyd@kernel.org: Fixup kernel-doc notation]
Reviewed-by: Niklas Cassel <nks@flawful.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04 23:08:17 -08:00
Maxime Ripard
9c232d324b
clk: sunxi: a23/a33: Export the MIPI PLL
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
headers.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04 09:45:19 +01:00
Maxime Ripard
a655ede064
clk: sunxi: a31: Export the MIPI PLL
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
headers.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04 09:45:09 +01:00
Vasily Khoruzhick
a9b5c67178
clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
Export CLK_CPUX so we can reference it in CPU node.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04 09:18:08 +01:00
Icenowy Zheng
ec97faff74
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.

Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.

Fixes: c6a0637460 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04 09:17:06 +01:00
Chen-Yu Tsai
b406cadbc8
clk: sunxi-ng: r40: Export MBUS clock
The MBUS clock needs to be referenced in the MBUS device node.
Export it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-03 10:37:14 +01:00
Samuel Holland
0c545240ae
clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order
According to the BSP source code, both the AR100 and R_APB2 clocks have
PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre-
divider used for PLL_PERIPH0 should be changed to index 3 to match.

This was verified by running a rough benchmark on the AR100 with various
clock settings:

        | mux | pre-divider | iterations/second | clock source |
        |=====|=============|===================|==============|
        |   0 |           0 |  19033   (stable) |       osc24M |
        |   2 |           5 |  11466 (unstable) |  iosc/osc16M |
        |   2 |          17 |  11422 (unstable) |  iosc/osc16M |
        |   3 |           5 |  85338   (stable) |  pll-periph0 |
        |   3 |          17 |  27167   (stable) |  pll-periph0 |

The relative performance numbers all match up (with pll-periph0 running
at its default 600MHz).

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-02 10:28:47 +01:00
Samuel Holland
675a6d467b
clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
Like the APB0 clock on previous chips, this is a simple single-parent
clock with an M divider. Use the equivalent helper macro instead of
writing out the whole clock description manually.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-02 10:27:56 +01:00
Samuel Holland
47d64fef1f
clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-02 10:27:47 +01:00
Guenter Roeck
12ead77432 clk: Don't try to enable critical clocks if prepare failed
The following traceback is seen if a critical clock fails to prepare.

bcm2835-clk 3f101000.cprman: plld: couldn't lock PLL
------------[ cut here ]------------
Enabling unprepared plld_per
WARNING: CPU: 1 PID: 1 at drivers/clk/clk.c:1014 clk_core_enable+0xcc/0x2c0
...
Call trace:
 clk_core_enable+0xcc/0x2c0
 __clk_register+0x5c4/0x788
 devm_clk_hw_register+0x4c/0xb0
 bcm2835_register_pll_divider+0xc0/0x150
 bcm2835_clk_probe+0x134/0x1e8
 platform_drv_probe+0x50/0xa0
 really_probe+0xd4/0x308
 driver_probe_device+0x54/0xe8
 device_driver_attach+0x6c/0x78
 __driver_attach+0x54/0xd8
...

Check return values from clk_core_prepare() and clk_core_enable() and
bail out if any of those functions returns an error.

Cc: Jerome Brunet <jbrunet@baylibre.com>
Fixes: 99652a469d ("clk: migrate the count of orphaned clocks at init")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lkml.kernel.org/r/20191225163429.29694-1-linux@roeck-us.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-26 13:59:34 -08:00
Sudeep Holla
43998dfe24 clk: scmi: Match scmi device by both name and protocol id
The scmi bus now has support to match the driver with devices not only
based on their protocol id but also based on their device name if one is
available. This was added to cater the need to support multiple devices
and drivers for the same protocol.

Let us add the name "clocks" to scmi_device_id table in the driver so
that in matches only with device with the same name and protocol id
SCMI_PROTOCOL_CLOCK.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-12-24 11:36:46 +00:00
YueHaibing
59ef4da4e4 clk: bm1800: Remove set but not used variable 'fref'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/clk/clk-bm1880.c: In function 'bm1880_pll_rate_calc':
drivers/clk/clk-bm1880.c:477:13: warning:
 variable 'fref' set but not used [-Wunused-but-set-variable]

It is never used, so remove it.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191129033534.188257-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24 00:10:33 -08:00
Dmitry Osipenko
fc666936f3 clk: tegra: Fix double-free in tegra_clk_init()
It's unlikely to happen in practice ever, but makes static checkers happy.

Fixes: 535f296d47 ("clk: tegra: Add suspend and resume support on Tegra210")
Reported-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lkml.kernel.org/r/20191210020512.6088-1-digetx@gmail.com
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24 00:01:06 -08:00
Marek Szyprowski
67f96ff7c8 clk: samsung: exynos5420: Keep top G3D clocks enabled
In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power
domain. This is similar to the other hardware modules and their power
domains. However there is one thing specific to G3D clocks hierarchy.
Unlike other hardware modules, the G3D clocks hierarchy doesn't have any
gate clock between the TOP part of the hierarchy and the part located in
the power domain and some SoC internal busses are sourced directly from
the TOP muxes. The consequence of this design if the fact that the TOP
part of the hierarchy has to be enabled permanently to ensure proper
operation of the SoC power related components (G3D power domain and
Exynos Power Management Unit for system suspend/resume).

This patch adds an explicit call to clk_prepare_enable() on the last MUX
in the TOP part of G3D clock hierarchy to keep it enabled permanently to
ensure that the internal busses get their clock regardless of the main
G3D clock enablement status.

This fixes following imprecise abort issue observed on Odroid XU3/XU4
after enabling Panfrost driver by commit 1a5a85c564 "ARM: dts: exynos:
Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"):

panfrost 11800000.gpu: clock rate = 400000000
panfrost 11800000.gpu: failed to get regulator: -517
panfrost 11800000.gpu: regulator init failed -517
Power domain G3D disable failed
...
panfrost 11800000.gpu: clock rate = 400000000
8<--- cut here ---
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
pgd = (ptrval)
[00000000] *pgd=00000000
Internal error: : 1406 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
Workqueue: events deferred_probe_work_func
PC is at panfrost_gpu_soft_reset+0x94/0x110
LR is at ___might_sleep+0x128/0x2dc
...
[<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c)
[<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc)
[<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178)
[<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c)
[<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474)
[<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc)
[<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8)
[<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c)
[<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90)
[<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0)
[<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864)
[<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0)
[<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160)
[<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
Exception stack(0xee03dfb0 to 0xee03dff8)
...
Code: e594300c e5933020 e3130c01 1a00000f (ebefff50).
---[ end trace badde2b74a65a540 ]---

In the above case, the Panfrost driver disables G3D clocks after failure
of getting the needed regulator and return with -EPROVE_DEFER code. This
causes G3D power domain disable failure and then, during second probe
an imprecise abort is triggered due to undefined power domain state.

Fixes: 45f10dabb5 ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path")
Fixes: c9f7567aff ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lkml.kernel.org/r/20191216131407.17225-1-m.szyprowski@samsung.com
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 23:50:57 -08:00
Taniya Das
dd3d066221 clk: qcom: Add display clock controller driver for SC7180
Add support for the display clock controller found on SC7180
based devices. This would allow display drivers to probe and
control their clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812245-23827-4-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 22:30:10 -08:00
Taniya Das
691865bad6 clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
In the cases where the PLL is not calibrated the PLL could fail to lock.
Add support for prepare ops which would take care of the same.

Fabia PLL user/test control registers might required to be configured, so
add support for configuring them.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812304-24074-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 22:30:09 -08:00
Taniya Das
1dc3698354 clk: qcom: alpha-pll: Remove useless read from set rate
PLL_MODE read in fabia set rate is not required, thus remove the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812304-24074-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 22:30:09 -08:00
Jerome Brunet
f873744c29 clk: add terminate callback to clk_ops
Add a terminate callback to the clk_ops to release the resources
claimed in .init()

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190924123954.31561-4-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 18:53:13 -08:00
Jerome Brunet
89d079dc17 clk: let init callback return an error code
If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 18:53:13 -08:00
Jerome Brunet
f6fa75ca91 clk: actually call the clock init before any other callback of the clock
__clk_init_parent() will call the .get_parent() callback of the clock
 so .init() must run before.

Fixes: 541debae0a ("clk: call the clock init() callback before any other ops callback")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190924123954.31561-2-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 18:53:13 -08:00
Jeffrey Hugo
db2c7c0a04 clk: qcom: Add missing msm8998 gcc_bimc_gfx_clk
gcc_bimc_gfx_clk is a required clock for booting the GPU and GPU SMMU.

Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20191217164913.4783-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23 18:24:48 -08:00
Peng Fan
b9ef22e159 clk: imx: imx8mq: Switch to clk_hw based API
Switch the entire clk-imx8mq driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:51:01 +08:00
Peng Fan
9c71f9ea35 clk: imx: imx8mm: Switch to clk_hw based API
Switch the entire clk-imx8mm driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:59 +08:00
Peng Fan
daeb145455 clk: imx: imx8mn: Switch to clk_hw based API
Switch the entire clk-imx8mn driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:56 +08:00
Peng Fan
44fa471087 clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
Some of i.MX SoCs' clock driver will use platform driver model,
and they need to call imx_obtain_fixed_clk_hw() API, so
imx_obtain_fixed_clk_hw() API should NOT be in .init section.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:54 +08:00
Peng Fan
02cb0228e9 clk: imx: gate3: Switch to clk_hw based API
Switch the imx_clk_hw_gate3_flags function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:51 +08:00
Peng Fan
3d43f1582c clk: imx: add hw API imx_clk_hw_mux2_flags
Introduce hw based API imx_clk_hw_mux2_flags, then we could
convert i.MX8MN clk driver to use hw based APIs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:49 +08:00
Peng Fan
61f35728ba clk: imx: add imx_unregister_hw_clocks
There is a non hw API based imx_unregister_clocks to unregister clocks
when of_clk_add_provider failed. Add a hw API based
imx_unregister_hw_clocks when of_clk_add_hw_provider failed.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:47 +08:00
Peng Fan
a4b431f803 clk: imx: clk-composite-8m: Switch to clk_hw based API
Switch the imx8m_clk_hw_composite_flags function to clk_hw based API,
rename accordingly and add a macro for clk based legacy. This allows
us to move closer to a clear split between consumer and provider clk
APIs.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:44 +08:00
Peng Fan
10c34b50f2 clk: imx: clk-pll14xx: Switch to clk_hw based API
Switch the imx_clk_pll14xx function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23 11:50:30 +08:00
Chris Brandt
c9d9d90347 clk: renesas: r7s9210: Add SPIBSC clock
Add SPIBSC clock for RZ/A2.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Link: https://lore.kernel.org/r/20191206134202.18784-4-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-20 15:03:27 +01:00
Sergei Shtylyov
0d67c0340a clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...

Fixes: db4a0073cc ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-20 15:02:15 +01:00
Jorge Ramirez-Ortiz
1ea7d2ca7b clk: qcom: apcs-msm8916: silently error out on EPROBE_DEFER
If devm_clk_get() fails due to probe deferral, we shouldn't print an
error message. Just be silent in this case.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20191125135910.679310-7-niklas.cassel@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:07:52 -08:00
Jorge Ramirez-Ortiz
8a7729abec clk: qcom: hfpll: use clk_parent_data to specify the parent
This permits extending the driver to other platforms without having to
modify its source code.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20191125135910.679310-6-niklas.cassel@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:07:52 -08:00
Jorge Ramirez-Ortiz
b455dc3510 clk: qcom: hfpll: CLK_IGNORE_UNUSED
When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
to keep the software model of the clock in line with reality, the
framework transverses the clock tree and disables those clocks that
were enabled by the firmware but have not been enabled by any device
driver.

If CPUFREQ is enabled, early during the system boot, it might attempt
to change the CPU frequency ("set_rate"). If the HFPLL is selected as
a provider, it will then change the rate for this clock.

As boot continues, clk_disable_unused_subtree will run. Since it wont
find a valid counter (enable_count) for a clock that is actually
enabled it will attempt to disable it which will cause the CPU to
stop. Notice that in this driver, calls to check whether the clock is
enabled are routed via the is_enabled callback which queries the
hardware.

The following commit, rather than marking the clock critical and
forcing the clock to be always enabled, addresses the above scenario
making sure the clock is not disabled but it continues to rely on the
firmware to enable the clock.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20191125135910.679310-5-niklas.cassel@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:07:52 -08:00
Jorge Ramirez-Ortiz
9e4066748b clk: qcom: hfpll: register as clock provider
Make the output of the high frequency pll a clock provider.
On the QCS404 this PLL controls cpu frequency scaling.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20191125135910.679310-4-niklas.cassel@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:07:52 -08:00
Jorge Ramirez-Ortiz
4168c1cada clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
specifications.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20191125135910.679310-3-niklas.cassel@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:07:52 -08:00
Jeffrey Hugo
87ec9adcca clk: qcom: smd: Add missing bimc clock
It turns out booting the modem is dependent on a bimc vote from Linux on
msm8998.  To make the modem happy, add the bimc clock to rely on the
default vote from rpmcc.  Once we have interconnect support, bimc should
be controlled properly.

Fixes: 6131dc8121 ("clk: qcom: smd: Add support for MSM8998 rpm clocks")
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20191217165409.4919-1-jeffrey.l.hugo@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:03:02 -08:00
Jeffrey Hugo
781d8cea68 clk: qcom: Avoid SMMU/cx gdsc corner cases
Mark the msm8998 cpu CX gdsc as votable and use the hw control to avoid
corner cases with SMMU per hardware documentation.

Fixes: 3f7df5baa2 ("clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver")
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20191217171905.5619-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 22:02:27 -08:00
Jeffrey Hugo
d14b15b593 clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver
Add a driver for the multimedia clock controller found on MSM8998
based devices. This should allow most multimedia device drivers
to probe and control their clocks.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/1576596033-10189-1-git-send-email-jhugo@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 21:37:40 -08:00
Matthias Kaehlcke
8d20c39f06 clk: qcom: gcc-sc7180: Fix setting flag for votable GDSCs
Commit 17269568f7 ("clk: qcom: Add Global Clock controller (GCC)
driver for SC7180") sets the VOTABLE flag in .pwrsts, but it needs
to be set in .flags, fix this.

Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lkml.kernel.org/r/20191204120341.1.I9971817e83ee890d1096c43c5a6ce6ced53d5bd3@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 21:35:58 -08:00
Brian Masney
bb9b9cde0f clk: qcom: mmcc8974: move gfx3d_clk_src from the mmcc to rpm
gfx3d_clk_src for msm8974 was introduced into the MMCC by
commit d8b212014e ("clk: qcom: Add support for MSM8974's multimedia
clock controller (MMCC)") to ensure that all of the clocks for
this platform are documented upstream. This clock actually belongs
on the RPM. Since then, commit 685dc94b7d ("clk: qcom: smd-rpmcc:
Add msm8974 clocks") was introduced, which contains the proper
definition for gfx3d_clk_src. Let's drop the definition from the
mmcc and register the clock with the rpm instead.

This change was tested on a Nexus 5 (hammerhead) phone.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lkml.kernel.org/r/20191115123931.18919-1-masneyb@onstation.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 21:27:44 -08:00
Taniya Das
c1079b4ec1 clk: qcom: dispcc: Add support for display port clocks
SDM845 dispcc supports RCG and CBCRs for display port, so add support for
the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190731182713.8123-3-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 21:24:13 -08:00
Taniya Das
cddf1f8241 clk: qcom: rcg2: Add support for display port clock ops
New display port clock ops supported for display port clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190731182713.8123-2-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 21:22:00 -08:00
Chen-Yu Tsai
c7b305267e
clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs
One of the uses of the external clock outputs is to provide a stable
32768 Hz clock signal to WiFi and Bluetooth chips. On the R40, the RTC
has an internal RC oscillator that is muxed with the external crystal.

Allow setting the parent rate for the external clock outputs so that
requests for 32768 Hz get passed to the RTC's clock driver to mux in
the external crystal if it isn't already muxed correctly.

Fixes: cd030a78f7 ("clk: sunxi-ng: support R40 SoC")
Fixes: 01a7ea763f ("clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output")
Cc: <stable@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-18 23:06:51 +01:00
Olof Johansson
c771256ee7 clk: Move clk_core_reparent_orphans() under CONFIG_OF
A recent addition exposed a helper that is only used for CONFIG_OF. Move
it into the CONFIG_OF zone in this file to make the compiler stop
warning about an unused function.

Fixes: 66d9506440 ("clk: walk orphan list on clock provider registration")
Signed-off-by: Olof Johansson <olof@lixom.net>
Link: https://lkml.kernel.org/r/20191217082501.424892072D@mail.kernel.org
[sboyd@kernel.org: "Simply" move the function instead]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18 10:16:30 -08:00
Alexandre Belloni
6956eb33ab clk: at91: fix possible deadlock
Lockdep warns about a possible circular locking dependency because using
syscon_node_to_regmap() will make the created regmap get and enable the
first clock it can parse from the device tree. This clock is not needed to
access the registers and should not be enabled at that time.

Use the recently introduced device_node_to_regmap to solve that as it looks
up the regmap in the same list but doesn't care about the clocks.

Reported-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20191128102531.817549-1-alexandre.belloni@bootlin.com
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-16 09:56:18 -08:00
Jerome Brunet
c97fcd8546 Merge branch 'v5.5/fixes' into v5.6/drivers 2019-12-16 10:59:26 +01:00
Remi Pommarel
d8488a4180 clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
Some meson pll registers can be initialized with 0 as N value, introducing
the following division by 0 when computing rate :

  UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9
  division by zero
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400
  Call trace:
   dump_backtrace+0x0/0x1c0
   show_stack+0x14/0x20
   dump_stack+0xc4/0x100
   ubsan_epilogue+0x14/0x68
   __ubsan_handle_divrem_overflow+0x98/0xb8
   __pll_params_to_rate+0xdc/0x140
   meson_clk_pll_recalc_rate+0x278/0x3a0
   __clk_register+0x7c8/0xbb0
   devm_clk_hw_register+0x54/0xc0
   meson_eeclkc_probe+0xf4/0x1a0
   platform_drv_probe+0x54/0xd8
   really_probe+0x16c/0x438
   driver_probe_device+0xb0/0xf0
   device_driver_attach+0x94/0xa0
   __driver_attach+0x70/0x108
   bus_for_each_dev+0xd8/0x128
   driver_attach+0x30/0x40
   bus_add_driver+0x1b0/0x2d8
   driver_register+0xbc/0x1d0
   __platform_driver_register+0x78/0x88
   axg_driver_init+0x18/0x20
   do_one_initcall+0xc8/0x24c
   kernel_init_freeable+0x2b0/0x344
   kernel_init+0x10/0x128
   ret_from_fork+0x10/0x18

This checks if N is null before doing the division.

Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
[jbrunet@baylibre.com: update the comment in above the fix]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-16 10:58:57 +01:00
Jerome Brunet
b1b3f0622a clk: meson: g12a: fix missing uart2 in regmap table
UART2 peripheral is missing from the regmap fixup table of the g12a family
clock controller. As it is, any access to this clock would Oops, which is
not great.

Add the clock to the table to fix the problem.

Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Reported-by: Dmitry Shmidt <dimitrysh@google.com>
Tested-by: Dmitry Shmidt <dimitrysh@google.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-16 10:28:38 +01:00
Geert Uytterhoeven
03975b72b4 clk: renesas: Remove use of ARCH_R8A7796
CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit
39e57e14d7 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car
M3-W"), so its users can be removed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191211100220.6854-1-geert+renesas@glider.be
2019-12-13 14:33:59 +01:00
Stephen Boyd
d3ab06f432 i.MX clock fixes for 5.5:
- Add missing lock to divider in the composite driver for exclusive
    register access.
  - Add missing sentinel for ulp_div_table in clk-imx7ulp driver.
  - Fix clk_pll14xx_wait_lock() function which calls into
    readl_poll_timeout() with incorrect parameter.
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Merge tag 'imx-clk-fixes-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

Pull i.MX clk fixes from Shawn Guo:

 - Add missing lock to divider in the composite driver for exclusive
   register access
 - Add missing sentinel for ulp_div_table in clk-imx7ulp driver
 - Fix clk_pll14xx_wait_lock() function which calls into
   readl_poll_timeout() with incorrect parameter

* tag 'imx-clk-fixes-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: pll14xx: fix clk_pll14xx_wait_lock
  clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table
  clk: imx: clk-composite-8m: add lock to gate/mux
2019-12-12 19:00:34 -08:00
Jerome Brunet
66d9506440 clk: walk orphan list on clock provider registration
So far, we walked the orphan list every time a new clock was registered
in CCF. This was fine since the clocks were only referenced by name.

Now that the clock can be referenced through DT, it is not enough:
* Controller A register first a reference clocks from controller B
  through DT.
* Controller B register all its clocks then register the provider.

Each time controller B registers a new clock, the orphan list is walked
but it can't match since the provider is registered yet. When the
provider is finally registered, the orphan list is not walked unless
another clock is registered afterward.

This can lead to situation where some clocks remain orphaned even if
the parent is available.

Walking the orphan list on provider registration solves the problem.

Reported-by: Jian Hu <jian.hu@amlogic.com>
Fixes: fc0c209c14 ("clk: Allow parents to be specified without string names")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20191203080805.104628-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-12 18:54:08 -08:00
Martin Blumenstingl
3bf258e159 clk: meson: meson8b: use of_clk_hw_register to register the clocks
Switch from clk_hw_register to of_clk_hw_register so we can use
clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll"
and possibly others from the .dtb.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11 14:06:31 +01:00
Martin Blumenstingl
096f0a2edf clk: meson: meson8b: don't register the XTAL clock when provided via OF
The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock
driver should not register the XTAL clock - instead it should be
provided via .dts and then passed to the clock controller.

Skip the registration of the XTAL clock if a parent clock is provided
via OF. Fall back to registering the XTAL clock if this is not the case
to keep support for old .dtbs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11 14:06:31 +01:00