Commit Graph

156 Commits

Author SHA1 Message Date
Manivannan Sadhasivam 7f83a13279 clocksource/drivers/rda: Add clock driver for RDA8810PL SoC
Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER
and HWTIMER.

RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER
(64 bit). Each timer provides optional interrupt support. In this
driver, OSTIMER is used for clockevents and HWTIMER is used for
clocksource.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Daniel Lezcano adab4ec3c2 clocksource/drivers/meson6: Change name meson6_timer timer-meson6
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Daniel Lezcano 493d09b7a7 clocksource/drivers/sun4i: Change name sun4i_timer to timer-sun4i
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Daniel Lezcano f155ae2c35 clocksource/drivers/tegra20: Change name tegra20_timer to timer-tegra20
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Daniel Lezcano 2d3bc644dd clocksource/drivers/rockchip: Change name rockchip_timer to timer-rockchip
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Daniel Lezcano 3d42b32b1d clocksource/drivers/riscv: Change name riscv_timer to timer-riscv
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18 22:22:23 +01:00
Linus Torvalds 35e7452442 Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull more timer updates from Thomas Gleixner:
 "A set of commits for the new C-SKY architecture timers"

* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  dt-bindings: timer: gx6605s SOC timer
  clocksource/drivers/c-sky: Add gx6605s SOC system timer
  dt-bindings: timer: C-SKY Multi-processor timer
  clocksource/drivers/c-sky: Add C-SKY SMP timer
2018-11-04 08:15:15 -08:00
Guo Ren 33745c3cc5 clocksource/drivers/c-sky: Add gx6605s SOC system timer
The driver is for gx6605s SOC system timer and there are two
same timers in gx6605s. We use one for clkevt and another one for
clksrc.

The timer is mmio map to access, so we need give mmio address in dts.

The counter at 0x0  offset is clock event.
The counter at 0x40 offset is clock source.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-11-02 19:41:12 +01:00
Guo Ren a7ad38b0dd clocksource/drivers/c-sky: Add C-SKY SMP timer
The driver is for C-SKY SMP timer. It only supports oneshot event
and 32bit overflow for clocksource. Per cpu core has one timer and
all timers share one clock-counter-input from the same clocksource.

This use mfcr&mtcr instructions to access the regs.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-11-02 19:39:54 +01:00
Daniel Lezcano 9d8d47ea6e clocksource/drivers: Unify the names to timer-* format
In order to make some housekeeping in the directory, this patch renames
drivers to the timer-* format in order to unify their names.

There is no functional changes.

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-10-03 14:37:02 +02:00
Linus Torvalds 1009aa1205 RISC-V Updates for the 4.19 Merge Window
This tag contains some major improvements to the RISC-V port, including
 the necessary interrupt controller and timer support to actually make it
 to userspace.  Support for three devices has been added:
 
 * Support for the ISA-mandated timers on RISC-V systems.
 * Support for the ISA-mandated first-level interrupt controller on
   RISC-V systems, which is handled as part of our core arch code because
   it's very small and tightly tied to the ISA.
 * Support for SiFive's platform-level interrupt controller, which talks
   to the actual devices.
 
 In addition to these new devices, there are a handful of cleanups all
 over the RISC-V tree:
 
 * Build fixes for various configurations
     * A fix to the vDSO build's makefile so it respects CFLAGS.
     * The addition of __lshrti3, a libgcc derived function necessary for
       some 32-bit configurations.
     * !SMP && PERF_EVENTS
 * Cleanups to the arch code to remove the remnants of old versions of
   the drivers that were just properly submitted.
     * Some dead code from the timer driver, most of which wasn't ever
       even compiled.
     * Cleanups of some interrupt #defines, which are now local to the
       interrupt handling code.
 * Fixes to ptrace(), which while not being sufficient to fully make GDB
   work are at least sufficient to get simple GDB tasks to work.
 * Early printk support via RISC-V's architecturally mandated SBI console
   device.
 * A fix to our early debug trap handler to ensure it's always aligned.
 
 These patches have all been through a fairly extensive review process,
 but as this enables a whole pile of functionality (ie, userspace) I'm
 confident we'll need to submit a few more patches.  The only concrete
 issues I know about are the sys_riscv_flush_icache patches, but as I
 managed to screw those up on Friday I figured it'd be best to let them
 bake another week.
 
 This tag boots a Fedora root filesystem on QEMU's master branch for me,
 and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
 the HiFive Unleashed.
 
 Thanks to Christoph Hellwig and the other guys at WD for getting the new
 drivers in shape!
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Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V updates from Palmer Dabbelt:
 "This contains some major improvements to the RISC-V port, including
  the necessary interrupt controller and timer support to actually make
  it to userspace. Support for three devices has been added:

   - the ISA-mandated timers on RISC-V systems.

   - the ISA-mandated first-level interrupt controller on RISC-V
     systems, which is handled as part of our core arch code because
     it's very small and tightly tied to the ISA.

   - SiFive's platform-level interrupt controller, which talks to the
     actual devices.

  In addition to these new devices, there are a handful of cleanups all
  over the RISC-V tree:

   - build fixes for various configurations:
      * A fix to the vDSO build's makefile so it respects CFLAGS.
      * The addition of __lshrti3, a libgcc derived function necessary
        for some 32-bit configurations.
      * !SMP && PERF_EVENTS

   - Cleanups to the arch code to remove the remnants of old versions of
     the drivers that were just properly submitted.
      * Some dead code from the timer driver, most of which wasn't ever
        even compiled.
      * Cleanups of some interrupt #defines, which are now local to the
        interrupt handling code.

   - Fixes to ptrace(), which while not being sufficient to fully make
     GDB work are at least sufficient to get simple GDB tasks to work.

   - Early printk support via RISC-V's architecturally mandated SBI
     console device.

   - A fix to our early debug trap handler to ensure it's always
     aligned.

  These patches have all been through a fairly extensive review process,
  but as this enables a whole pile of functionality (ie, userspace) I'm
  confident we'll need to submit a few more patches. The only concrete
  issues I know about are the sys_riscv_flush_icache patches, but as I
  managed to screw those up on Friday I figured it'd be best to let them
  bake another week.

  This tag boots a Fedora root filesystem on QEMU's master branch for
  me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
  on the HiFive Unleashed.

  Thanks to Christoph Hellwig and the other guys at WD for getting the
  new drivers in shape!"

* tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
  dt-bindings: interrupt-controller: RISC-V local interrupt controller
  RISC-V: Fix !CONFIG_SMP compilation error
  irqchip: add a SiFive PLIC driver
  RISC-V: Add the directive for alignment of stvec's value
  clocksource: new RISC-V SBI timer driver
  RISC-V: implement low-level interrupt handling
  RISC-V: add a definition for the SIE SEIE bit
  RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
  RISC-V: simplify software interrupt / IPI code
  RISC-V: remove timer leftovers
  RISC-V: Add early printk support via the SBI console
  RISC-V: Don't increment sepc after breakpoint.
  RISC-V: implement __lshrti3.
  RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
2018-08-19 09:56:38 -07:00
Palmer Dabbelt 62b0194368
clocksource: new RISC-V SBI timer driver
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems.  The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.

Contains various improvements from Atish Patra <atish.patra@wdc.com>.

Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
[hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
 minor cleanups, merged  hotplug cpu support and other improvements
 from Atish]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 08:31:31 -07:00
Stanley Chu 7ec58e5244 clocksource/drivers/timer-mediatek: Rename mtk_timer to timer-mediatek
Rename mtk_timer to timer-mediatek to apply new naming convention
in clocksource folder.

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-07-26 11:26:32 +02:00
Linus Torvalds d95c884439 Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull missed timer updates from Thomas Gleixner:
 "This is a branch which got forgotten during the merge window, but it
  contains only fixes and hardware enablement. No fundamental changes.

   - Various fixes for the imx-tpm clocksource driver

   - A new timer driver for the NCPM7xx SoC family"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource/drivers/imx-tpm: Add different counter width support
  clocksource/drivers/imx-tpm: Correct some registers operation flow
  clocksource/drivers/imx-tpm: Fix typo of clock name
  dt-bindings: timer: tpm: fix typo of clock name
  clocksource/drivers/npcm: Add NPCM7xx timer driver
  dt-binding: timer: document NPCM7xx timer DT bindings
2018-04-16 12:44:03 -07:00
Linus Torvalds 167569343f ARM: SoC platform updates for 4.17
This release brings up a new platform based on the old ARM9 core: the
 Nuvoton NPCM is used as a baseboard management controller, competing
 with the better known ASpeed AST2xx series.
 
 Another important change is the addition of ARMv7-A based chips
 in mach-stm32. The older parts in this platform are ARMv7-M based
 microcontrollers, now they are expanding to general-purpose workloads.
 
 The other changes are the usual defconfig updates to enable additional
 drivers, lesser bugfixes. The largest updates as often are the ongoing
 OMAP cleanups, but we also have a number of changes for the older
 PXA and davinci platforms this time.
 
 For the Renesas shmobile/r-car platform, some new infrastructure
 is needed to make the watchdog work correctly.
 
 Supporting Multiprocessing on Allwinner A80 required a significant
 amount of new code, but is not doing anything unexpected.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "This release brings up a new platform based on the old ARM9 core: the
  Nuvoton NPCM is used as a baseboard management controller, competing
  with the better known ASpeed AST2xx series.

  Another important change is the addition of ARMv7-A based chips in
  mach-stm32. The older parts in this platform are ARMv7-M based
  microcontrollers, now they are expanding to general-purpose workloads.

  The other changes are the usual defconfig updates to enable additional
  drivers, lesser bugfixes. The largest updates as often are the ongoing
  OMAP cleanups, but we also have a number of changes for the older PXA
  and davinci platforms this time.

  For the Renesas shmobile/r-car platform, some new infrastructure is
  needed to make the watchdog work correctly.

  Supporting Multiprocessing on Allwinner A80 required a significant
  amount of new code, but is not doing anything unexpected"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits)
  arm: npcm: modify configuration for the NPCM7xx BMC.
  MAINTAINERS: update entry for ARM/berlin
  ARM: omap2: fix am43xx build without L2X0
  ARM: davinci: da8xx: simplify CFGCHIP regmap_config
  ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data
  ARM: multi_v7_defconfig: add NXP FlexCAN IP support
  ARM: multi_v7_defconfig: enable thermal driver for i.MX devices
  ARM: multi_v7_defconfig: add RN5T618 PMIC family support
  ARM: multi_v7_defconfig: add NXP graphics drivers
  ARM: multi_v7_defconfig: add GPMI NAND controller support
  ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs
  ARM: multi_v7_defconfig: configure I2C driver built-in
  arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE
  ARM: imx: fix imx6sll-only build
  ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well
  ARM: mxs_defconfig: Re-sync defconfig
  ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver
  ARM: imx_v4_v5_defconfig: Re-sync defconfig
  arm64: defconfig: enable stmmac ethernet to defconfig
  ARM: EXYNOS: Simplify code in coupled CPU idle hot path
  ...
2018-04-05 21:21:08 -07:00
Linus Torvalds f5a8eb632b arch: remove obsolete architecture ports
This removes the entire architecture code for blackfin, cris, frv, m32r,
 metag, mn10300, score, and tile, including the associated device drivers.
 
 I have been working with the (former) maintainers for each one to ensure
 that my interpretation was right and the code is definitely unused in
 mainline kernels. Many had fond memories of working on the respective
 ports to start with and getting them included in upstream, but also saw
 no point in keeping the port alive without any users.
 
 In the end, it seems that while the eight architectures are extremely
 different, they all suffered the same fate: There was one company
 in charge of an SoC line, a CPU microarchitecture and a software
 ecosystem, which was more costly than licensing newer off-the-shelf
 CPU cores from a third party (typically ARM, MIPS, or RISC-V). It seems
 that all the SoC product lines are still around, but have not used the
 custom CPU architectures for several years at this point. In contrast,
 CPU instruction sets that remain popular and have actively maintained
 kernel ports tend to all be used across multiple licensees.
 
 The removal came out of a discussion that is now documented at
 https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
 marking any ports as deprecated but remove them all at once after I made
 sure that they are all unused. Some architectures (notably tile, mn10300,
 and blackfin) are still being shipped in products with old kernels,
 but those products will never be updated to newer kernel releases.
 
 After this series, we still have a few architectures without mainline
 gcc support:
 
 - unicore32 and hexagon both have very outdated gcc releases, but the
   maintainers promised to work on providing something newer. At least
   in case of hexagon, this will only be llvm, not gcc.
 
 - openrisc, risc-v and nds32 are still in the process of finishing their
   support or getting it added to mainline gcc in the first place.
   They all have patched gcc-7.3 ports that work to some degree, but
   complete upstream support won't happen before gcc-8.1. Csky posted
   their first kernel patch set last week, their situation will be similar.
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Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...
2018-04-02 20:20:12 -07:00
Tomer Maimon 1c00289ecd clocksource/drivers/npcm: Add NPCM7xx timer driver
Add Nuvoton BMC NPCM7xx timer driver.

The clocksource Enable 24-bit TIMER0 and TIMER1 counters,
while TIMER0 serve as clockevent and TIMER1 serve as clocksource.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Brendan Higgins <brendanhiggins@xxxxxxxxxx>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-03-30 22:44:09 +02:00
James Hogan b79a732504
clocksource: Remove metag generic timer driver
Now that arch/metag/ has been removed, remove the metag generic
per-thread timer driver. It is of no value without the architecture
code.

Signed-off-by: James Hogan <jhogan@kernel.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-metag@vger.kernel.org
2018-02-23 14:30:20 +00:00
Keerthy af04aa856e ARM: OMAP: Move dmtimer driver out of plat-omap to drivers under clocksource
Move the dmtimer driver out of plat-omap to clocksource.
So that non-omap devices also could use this.

No Code changes done to the driver file only renamed to timer-ti-dm.c.
Also removed the config dependencies for OMAP_DM_TIMER.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
[tony@atomide.com: add select omap_dm_timer for omap16xx]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-02-22 10:53:52 -08:00
Rick Chen 35dbb74aa7 clocksource/drivers/atcpit100: Add andestech atcpit100 timer
ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Add andestech atcpit100 timer
2018-02-22 10:44:36 +08:00
Baolin Wang 067bc91447 clocksource/drivers/spreadtrum: Add timer driver for the Spreadtrum SC9860 platform
The Spreadtrum SC9860 platform will use the architected timers as local
clock events, but we also need a broadcast timer device to wake up the
CPUs when the CPUs are in sleep mode.

The Spreadtrum timer can support 32-bit or 64-bit counters, as well as
supporting period mode or one-shot mode.

Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1515418139-23276-8-git-send-email-daniel.lezcano@linaro.org
[ Minor readability edits. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-01-08 17:57:24 +01:00
Greg Kroah-Hartman b24413180f License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier.  The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
 - file had no licensing information it it.
 - file was a */uapi/* one with no licensing information in it,
 - file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne.  Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed.  Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
 - Files considered eligible had to be source code files.
 - Make and config files were included as candidates if they contained >5
   lines of source
 - File already had some variant of a license header in it (even if <5
   lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

 - when both scanners couldn't find any license traces, file was
   considered to have no license information in it, and the top level
   COPYING file license applied.

   For non */uapi/* files that summary was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0                                              11139

   and resulted in the first patch in this series.

   If that file was a */uapi/* path one, it was "GPL-2.0 WITH
   Linux-syscall-note" otherwise it was "GPL-2.0".  Results of that was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0 WITH Linux-syscall-note                        930

   and resulted in the second patch in this series.

 - if a file had some form of licensing information in it, and was one
   of the */uapi/* ones, it was denoted with the Linux-syscall-note if
   any GPL family license was found in the file or had no licensing in
   it (per prior point).  Results summary:

   SPDX license identifier                            # files
   ---------------------------------------------------|------
   GPL-2.0 WITH Linux-syscall-note                       270
   GPL-2.0+ WITH Linux-syscall-note                      169
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause)    21
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)    17
   LGPL-2.1+ WITH Linux-syscall-note                      15
   GPL-1.0+ WITH Linux-syscall-note                       14
   ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause)    5
   LGPL-2.0+ WITH Linux-syscall-note                       4
   LGPL-2.1 WITH Linux-syscall-note                        3
   ((GPL-2.0 WITH Linux-syscall-note) OR MIT)              3
   ((GPL-2.0 WITH Linux-syscall-note) AND MIT)             1

   and that resulted in the third patch in this series.

 - when the two scanners agreed on the detected license(s), that became
   the concluded license(s).

 - when there was disagreement between the two scanners (one detected a
   license but the other didn't, or they both detected different
   licenses) a manual inspection of the file occurred.

 - In most cases a manual inspection of the information in the file
   resulted in a clear resolution of the license that should apply (and
   which scanner probably needed to revisit its heuristics).

 - When it was not immediately clear, the license identifier was
   confirmed with lawyers working with the Linux Foundation.

 - If there was any question as to the appropriate license identifier,
   the file was flagged for further research and to be revisited later
   in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights.  The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
 - a full scancode scan run, collecting the matched texts, detected
   license ids and scores
 - reviewing anything where there was a license detected (about 500+
   files) to ensure that the applied SPDX license was correct
 - reviewing anything where there was no detection but the patch license
   was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
   SPDX license was correct

This produced a worksheet with 20 files needing minor correction.  This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg.  Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected.  This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.)  Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-02 11:10:55 +01:00
Dong Aisheng 059ab7b82e clocksource/drivers/imx-tpm: Add imx tpm timer support
IMX Timer/PWM Module (TPM) supports both timer and pwm function while
this patch only adds the timer support. PWM would be added later.

The TPM counter, compare and capture registers are clocked by an
asynchronous clock that can remain enabled in low power modes.

NOTE: We observed in a very small probability, the bus fabric
contention between GPU and A7 may results a few cycles delay
of writing CNT registers which may cause the min_delta event got
missed, so we need add a ETIME check here in case it happened.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-08-29 11:07:56 +02:00
Linus Torvalds e854711291 ARM: SoC driver updates
- New SoC specific drivers
   - NVIDIA Tegra PM Domain support for newer SoCs (Tegra186 and later)
     based on the "BPMP" firmware
   - Clocksource and system controller drivers for the newly added
     Action Semi platforms (both arm and arm64).
 
 - Reset subsystem, merged through arm-soc by tradition:
   - New drivers for Altera Stratix10, TI Keystone and Cortina Gemini SoCs
   - Various subsystem-wide cleanups
 
 - Updates for existing SoC-specific drivers
   - TI GPMC (General Purpose Memory Controller)
   - Mediatek "scpsys" system controller support for MT6797
   - Broadcom "brcmstb_gisb" bus arbitrer
   - ARM SCPI firmware
   - Renesas "SYSC" system controller
 
 One more driver update was submitted for the Freescale/NXP DPAA
 data path acceleration that has previously been used on PowerPC
 chips. I ended up postponing the merge until some API questions
 for its unusual MMIO access are resolved.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "New SoC specific drivers:

   - NVIDIA Tegra PM Domain support for newer SoCs (Tegra186 and later)
     based on the "BPMP" firmware

   - Clocksource and system controller drivers for the newly added
     Action Semi platforms (both arm and arm64).

  Reset subsystem, merged through arm-soc by tradition:

   - New drivers for Altera Stratix10, TI Keystone and Cortina Gemini
     SoCs

   - Various subsystem-wide cleanups

  Updates for existing SoC-specific drivers

   - TI GPMC (General Purpose Memory Controller)

   - Mediatek "scpsys" system controller support for MT6797

   - Broadcom "brcmstb_gisb" bus arbitrer

   - ARM SCPI firmware

   - Renesas "SYSC" system controller

  One more driver update was submitted for the Freescale/NXP DPAA data
  path acceleration that has previously been used on PowerPC chips. I
  ended up postponing the merge until some API questions for its unusual
  MMIO access are resolved"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits)
  clocksource: owl: Add S900 support
  clocksource: Add Owl timer
  soc: renesas: rcar-sysc: Use GENPD_FLAG_ALWAYS_ON
  firmware: tegra: Fix locking bugs in BPMP
  soc/tegra: flowctrl: Fix error handling
  soc/tegra: bpmp: Implement generic PM domains
  soc/tegra: bpmp: Update ABI header
  PM / Domains: Allow overriding the ->xlate() callback
  soc: brcmstb: enable drivers for ARM64 and BMIPS
  soc: renesas: Rework Kconfig and Makefile logic
  reset: Add the TI SCI reset driver
  dt-bindings: reset: Add TI SCI reset binding
  reset: use kref for reference counting
  soc: qcom: smsm: Improve error handling, quiesce probe deferral
  cpufreq: scpi: use new scpi_ops functions to remove duplicate code
  firmware: arm_scpi: add support to populate OPPs and get transition latency
  dt-bindings: reset: Add reset manager offsets for Stratix10
  memory: omap-gpmc: add error message if bank-width property is absent
  memory: omap-gpmc: make dts snippet include semicolon
  reset: Add a Gemini reset controller
  ...
2017-07-04 14:47:47 -07:00
Andreas Färber 4be78a86c5 clocksource: Add Owl timer
The Actions Semi S500 SoC provides four timers, 2Hz0/1 and 32-bit TIMER0/1.

Use TIMER0 as clocksource and TIMER1 as clockevents.

Based on LeMaker linux-actions tree.

An S500 datasheet can be found on the LeMaker Guitar pages:
http://www.lemaker.org/product-guitar-download-29.html

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2017-06-18 21:19:48 +02:00
Daniel Lezcano dc11bae785 clocksource/drivers: Add timer-of common init routine
The different drivers are all using the same pattern when initializing.

 1. Get the base address
 2. Get the irq number
 3. Get the clock
 4. Prepare and enable the clock
 5. Get the rate
 6. Request an interrupt

Instead of repeating again and again these steps in all the drivers, let's
provide a common init routine to give the opportunity to factor all of them
out.

We can expect a significant kernel size improvement when the common routine
will be used in all the drivers.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-06-14 12:02:32 +02:00
Daniel Lezcano bb0eb050a5 clocksource/drivers: Rename CLKSRC_OF to TIMER_OF
The config option name is now renamed to 'TIMER_OF' for consistency with
the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-14 12:01:03 +02:00
Daniel Lezcano 8e0931022e Revert "clockevents: Add a clkevt-of mechanism like clksrc-of"
After discussing it, this feature is dropped as it is not considered
adequate:

	https://patchwork.kernel.org/patch/9639317/

There is no user of this macro yet, so there is no impact on the drivers.

This reverts commit 376bc27150.

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-06-12 10:54:47 +02:00
Linus Walleij ec14ba1ec5 clocksource/drivers/fttmr010: Merge Moxa into FTTMR010
This merges the Moxa Art timer driver into the Faraday FTTMR010
driver and replaces all Kconfig symbols to use the Faraday
driver instead. We are now so similar that the drivers can
be merged by just adding a few lines to the Faraday timer.

Differences:

- The Faraday driver explicitly sets the counter to count
  upwards for the clocksource, removing the need for the
  clocksource core to invert the value.

- The Faraday driver also handles sched_clock()

On the Aspeed, the counter can only count downwards, so support
the timers in downward-counting mode as well, and flag the
Aspeed to use this mode. This mode was tested on the Gemini so
I have high hopes that it'll work fine on the Aspeed as well.

After this we have one driver for all three SoCs and a generic
Faraday FTTMR010 timer driver, which is nice.

Cc: Joel Stanley <joel@jms.id.au>
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-06-12 10:45:10 +02:00
Linus Walleij f5bf0ee4eb clocksource/drivers/gemini: Rename Gemini timer to Faraday
After some research it turns out that the "Gemini" timer is
actually a generic IP block from Faraday Technology named
FTTMR010, so as to not make things too confusing we need to
rename the driver and its symbols to make sense.

The implementation remains the same in this patch but we fix
the copy-paste error in the timer name "nomadik_mtu" as we're
at it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-04-07 16:23:08 +02:00
Chris Brandt fb6002a826 clocksource/drivers/ostm: Add renesas-ostm timer driver
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-02-07 20:58:30 +01:00
Linus Walleij 4750535bc9 clocksource/drivers/gemini: Add driver for the Cortina Gemini
This is a rewrite of the Gemini timer
driver in arch/arm/mach-gemini/timer.c trying to do everything
the device tree way:

- Make every IO-access relative to a base address and dynamic
  so we can do a dynamic ioremap and get going.
- Do not poke around directly in the global syscon registers,
  access them using the syscon regmap style design pattern for
  the one register we need to check.
- Find register range and interrupt from the device tree.

Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-02-07 20:58:30 +01:00
Daniel Lezcano 376bc27150 clockevents: Add a clkevt-of mechanism like clksrc-of
The current code uses the CLOCKSOURCE_OF_DECLARE macro to fill the clksrc
table with a t-uple (name, init_function).

Unfortunately it ends up to the clockevent and the clocksource being
both initialized with this macro. It is not a problem by itself but there
is not a clear distinction between a clockevent and a clocksource in the
code initialization path. Somebody can argue there are the same IP block
and the same DT node. But conceptually from the software side, there are
two distincts entities and as is they should be initialized separetely.
Some drivers which do not have a clocksource end up by using the
CLOCKSOURCE_OF_DECLARE macro to declare a clockevent.

Another result is the fuzzy organization in the clocksource directory,
where the clockevents are implemented in the same file than the
clocksources or file labelled timer-something implementing a clocksource.

This patch provides another macro to specifically declare a clockevent in
the same way than the clocksource and gives the opportunity to write two
separate drivers, one for the clocksource and another for the clockevents.

Hopefully, that can help to do some housework in the directory, perhaps
split the drivers in to entities, for example:
	- clksrc-rockchip.c
	- clkevt-rockchip.c

Also, it gives the possibility to declare clocksources separately in the
DT and then use a clocksource from IP block while while clockevents are
used from another IP block.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-02-07 20:58:30 +01:00
Vineet Gupta c4c9a040ec clocksource: import ARC timer driver
This adds support for

 - CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP
   from @CNT to @LIMIT, before optionally triggering an interrupt.
   These are programmed using ARC auxiliary register interface.
   These are present in all ARC cores (ARC700 and ARC HS38)
   TIMER0 serves as clockevent for all ARC linux builds.
   TIMER1 is used for clocksource in arc700 builds.

 - CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in
   ARC HS38 cores. These are independnet IP blocks with different
   programming model respectively.

Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-30 11:54:25 -08:00
Rich Felker 9995f4f184 clocksource: Add J-Core timer/clocksource driver
At the hardware level, the J-Core PIT is integrated with the interrupt
controller, but it is represented as its own device and has an
independent programming interface. It provides a 12-bit countdown
timer, which is not presently used, and a periodic timer. The interval
length for the latter is programmable via a 32-bit throttle register
whose units are determined by a bus-period register. The periodic
timer is used to implement both periodic and oneshot clock event
modes; in oneshot mode the interrupt handler simply disables the timer
as soon as it fires.

Despite its device tree node representing an interrupt for the PIT,
the actual irq generated is programmable, not hard-wired. The driver
is responsible for programming the PIT to generate the hardware irq
number that the DT assigns to it.

On SMP configurations, J-Core provides cpu-local instances of the PIT;
no broadcast timer is needed. This driver supports the creation of the
necessary per-cpu clock_event_device instances.

A nanosecond-resolution clocksource is provided using the J-Core "RTC"
registers, which give a 64-bit seconds count and 32-bit nanoseconds
that wrap every second. The driver converts these to a full-range
32-bit nanoseconds count.

Signed-off-by: Rich Felker <dalias@libc.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/b591ff12cc5ebf63d1edc98da26046f95a233814.1476393790.git.dalias@libc.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-10-20 20:10:17 +02:00
Daniel Lezcano 568c0342e4 clocksource/drivers/integrator-ap: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_INTEGRATOR_AP_TIMER and is selected
by the platform. Then the clocksource's Kconfig is changed to make this
option selectable by the user if the COMPILE_TEST option is set. Otherwise,
it is up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:16 +02:00
Daniel Lezcano c12547a00d clocksource/drivers/keystone: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_KEYSTONE_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:15 +02:00
Daniel Lezcano d683b9dcc8 clocksource/drivers/nspire: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_NSPIRE_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:14 +02:00
Daniel Lezcano 85f98db4ad clocksource/drivers/u300: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_U300_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Due on the delay specific code, this driver will compile only on the ARM
architecture.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:13 +02:00
Daniel Lezcano f3550d4995 clocksource/drivers/prima2: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_PRIMA2_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:12 +02:00
Daniel Lezcano d81c50a036 clocksource/drivers/mxs: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_MXS_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:10 +02:00
Daniel Lezcano 419be9e36c clocksource/drivers/moxart: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_MOXART_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:08 +02:00
Daniel Lezcano b56d5d2184 clocksource/drivers/atlas7: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_ATLAS7_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:08 +02:00
Daniel Lezcano ecf0efdc98 clocksource/drivers/clps_711x: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_CLPS711X_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:07 +02:00
Daniel Lezcano 1cad71e35f clocksource/drivers/bcm_kona: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_BCM_KONA_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it is
up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:06 +02:00
Daniel Lezcano 2ea879a7cf clocksource/drivers/bcm2835: Add the COMPILE_TEST option
Change the Kconfig option logic to fullfil with the current approach.

A new Kconfig option is added, CONFIG_BCM2835_TIMER and is selected by the
platform. Then the clocksource's Kconfig is changed to make this option
selectable by the user if the COMPILE_TEST option is set. Otherwise, it
is up to the platform's Kconfig to select the timer.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:22:04 +02:00
Neil Armstrong 89355274e1 clocksource/drivers/oxnas-rps: Add Oxford Semiconductor RPS Dual Timer
Add clocksource and clockevent driver from dual RPS timer.
The HW provides a dual one-shot or periodic 24bit timers,
the drivers set the first one as tick event source and the
second as a continuous scheduler clock source.
The timer can use 1, 16 or 256 as pre-dividers, thus the
clocksource uses 16 by default.

CC: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:17:10 +02:00
Linus Torvalds 0efacbbaee ARC updates for 4.7-rc1
- Support for EZChip (now Mellanox) NPS-400 Network processor based on ARC700
     http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf
 - NPS interrupt controller and clocksource drivers
 - ARC timers probed off DT
 - ARC iqrchips switching to linear domain (upgrade from legacy domains)
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Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:
 "We have a relatively big changeset for ARC for 4.7.

  The highlight is support for EZChip (now Mellanox) NPS-400 network
  processor, a 400-Gb throughput C-programmable packet processor based
  on ARC700 cores from Synopsys. See

        http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf

  Also present are irqchip and clocksource drivers for NPS as agreed
  with respective maintainers to go via ARC tree due to an soc header
  dependency.  I have the needed ACKs from Jason, Marc, Daniel.  You
  might run into a trivial merge conflict in drivers/irqchip/*

  This EZChip platform support required some deep changes in ARC
  architecture code and also opportunity to cleanup past sins (legacy
  irq domains, missing irq domain lookup, hard coded timer irqs...)

  Summary:

   - Support for EZChip (now Mellanox) NPS-400 Network processor based
     on ARC700

   - NPS interrupt controller and clocksource drivers

   - ARC timers probed off DT

   - ARC iqrchips switching to linear domain (upgrade from legacy
     domains)"

* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
  arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
  arc: axs10x: Add DT bindings for I2S PLL Clock
  ARC: pae: STRICT_MM_TYPECHECKS was broken
  ARC: Add eznps platform to Kconfig and Makefile
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: [plat-eznps] Use dedicated cpu_relax()
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: Mark secondary cpu online only after all HW setup is done
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Make vmalloc size configurable
  ARC: clean out UAPI byteorder.h clean off Kconfig symbol
  irqchip: add nps Internal and external irqchips
  clocksource: Add NPS400 timers driver
  soc: Support for EZchip SoC
  Documentation: Add EZchip vendor to binding list
  ...
2016-05-19 09:46:18 -07:00
Noam Camus a53224577e clocksource: Add NPS400 timers driver
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-05-09 09:32:31 +05:30
Vladimir Murzin 0302637f18 clockevents/driversi/mps2: add MPS2 Timer driver
MPS2 platform has simple 32 bits general purpose countdown timers.

The driver uses the first detected timer as a clocksource and the rest
of the timers as a clockevent

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-04-28 15:09:06 +02:00