Commit graph

54 commits

Author SHA1 Message Date
Tomoya MORINAGA
943d8d8bca dma : EG20T PCH: Fix miss-setting DMA descriptor
Currently, in case of using scatter/gather mode, head of data is not sent to

destination. The cause is second descriptor address is set to NEXT.

The NEXT must have head of descriptor address.

This patch sets head of descriptor address to the NEXT.

Acked-by: Yong Wang <youg.y.wang@intel.com>
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
[dan.j.williams@intel.com: fixed up usage of virt_to_phys()]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-12-07 15:07:08 -08:00
Dzianis Kahanovich
87acf5ad87 NULL-terminate all pci_device_id tables
NULL-terminating pci_device_id in pch_dma.c and scx200_acb.c
for appying MODULE_DEVICE_TABLE (to publish modalias-es).

Signed-off-by: Dzianis Kahanovich <mahatma@eu.by>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
2010-10-27 20:33:05 +10:30
Yong Wang
61cd220376 DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l
Use {read|write}l instead of __raw_{read|write}l since PCH DMA
controller is PCI device.

Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-08-04 22:08:45 -07:00
Yong Wang
0c42bd0e42 dmaengine: Driver for Topcliff PCH DMA controller
Topcliff PCH is the platform controller hub that is going to
be used in Intel's upcoming general embedded platforms. This
adds the driver for Topcliff PCH DMA controller. The DMA
channels are strictly for device to host or host to device
transfers and cannot be used for generic memcpy.

Signed-off-by: Yong Wang <yong.y.wang@intel.com>
[kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-08-04 14:12:05 -07:00