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Author SHA1 Message Date
jason-jh.lin
4e8988c634 soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0 
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.

But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220419094143.9561-7-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2022-04-22 14:38:53 +02:00
Rex-BC Chen
831785f0e5 soc: mediatek: mmsys: add mmsys reset control for MT8186 
Add mmsys reset control register 0x160 for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220217082626.15728-3-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2022-03-01 08:34:47 +01:00
Yongqiang Niu
5f9b5b757e soc: mediatek: mmsys: add mt8186 mmsys routing table 
Add new routing table for MT8186.
In MT8186, there are two routing pipelines for internal and external
display.

Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->
		  DITHER->DSI0
External display: OVL_2L0->RDMA1->DPI0

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2022-02-28 12:18:39 +01:00