Commit Graph

8 Commits

Author SHA1 Message Date
Alexey Klimov 11faa20eb4 clocksource/drivers/mtk_timer: Fix memleak in mtk_timer_init()
Add error path to clear evt struct allocated by kzalloc() in the beginning of
function mtk_timer_init().

Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-12-15 09:41:04 +01:00
Alexey Klimov 6cd7ccaaa8 clocksource/drivers/mtk_timer: Fix pr_warn() messages in mtk_timer_init
1) Change pr_warn()s to pr_err()s. These messages are actually errors and not
   warnings.
2) Add missing \n.
3) Error message for kzalloc() failure is removed per suggestion by Joe Perches.
   There is generic stack_dump() for allocation issues.

Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-12-15 09:41:02 +01:00
Alexey Klimov 9a78ec45bd clocksource/drivers/mtk_timer: Add pr_fmt define
It's a bit unclear what subsystem/driver emits some messages to dmesg in
the function mtk_init_timer(). Use pr_fmt to auto-prefix the messages
appropriately.

Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-12-15 09:41:00 +01:00
Yingjoe Chen f14665f63b clocksource/drivers/mediatek: Use GPT as sched clock source
When cpu is in deep idle, arch timer will stop counting. Setup GPT as
sched clock source so it can keep counting in idle.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-10-15 17:41:58 +02:00
Daniel Lezcano fc686d0037 clockevents/drivers/mtk: Fix spurious interrupt leading to crash
After analysis done by Yingjoe Chen, the timer appears to have a pending
interrupt when it is enabled.

Fix this by acknowledging the pending interrupt when enabling the timer
interrupt.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
2015-10-15 17:41:56 +02:00
Viresh Kumar a2b7e10d29 clockevents/drivers/mtk: Migrate to new 'set-state' interface
Migrate mtk driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

Cc: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-08-10 11:40:33 +02:00
Matthias Brugger d4a19eb3b1 clocksource: mtk: Fix race conditions in probe code
We have two race conditions in the probe code which could lead to a null
pointer dereference in the interrupt handler.

The interrupt handler accesses the clockevent device, which may not yet be
registered.

First race condition happens when the interrupt handler gets registered before
the interrupts get disabled. The second race condition happens when the
interrupts get enabled, but the clockevent device is not yet registered.

Fix that by disabling the interrupts before we register the interrupt and enable
the interrupts after the clockevent device got registered.

Reported-by: Gongbae Park <yongbae2@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-02-25 10:28:49 +01:00
Matthias Brugger ecb3530dd5 clocksource: Add support for the Mediatek SoCs
This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-07-23 12:02:31 +02:00