Makefile changes:
- enable unused-variable warning that was wrongly disabled for clang
Kconfig changes:
- warn blank 'help' and fix existing instances
- fix 'choice' behavior to not write out invisible symbols
- fix misc weirdness
Coccinell changes:
- fix false positive of free after managed memory alloc detection
- improve performance of NULL dereference detection
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJafl86AAoJED2LAQed4NsGrBEP/23mRl+8dSYkTmlczP7stZHL
tGkMQIOj85usPV4JIxYHgge6XhU0CBFXNGnDnxGeNEtwnBr5QQNxuS2nPh7rHJIN
zX5rX/vwO9lzn2FFEdKrk8bito1IgnUHUvN/d0ikPWzY7GaMy6WrIWgyThllsLNE
W7hp3cpUQOhLL9PKXwglZ/oS4iTpEs0DwN93UXU7cp7zyRa0XtFfPf7/IJ2KY+Yl
a2TEsUuZ/slJoxLhacr6+TBAgqUyewWIs0nAGdjP2EVlSjxZJQYFEQq4KnLUO2gV
wLHH2snsZSBDfPDp0M9OOb737HE17NRmuLjWxUZZOMFz8tvfUT1454zhVAN2OtSQ
cP0RqVRrFiS721oxacZpAxKFrd7o4ugUHpftJMPQAq70T9JFFbapfCLvd+OblOb/
CWmDOOR37tvop5OCuaqaSMq7a+ZQt2cO5fogiEDdnjZkk2AH5GgsAHJIrl7hH4OT
P9UMcxaWSGbutdVkM4cMUmYMuAJjiFhx1fiD+hevB1KvemXRXrqhCb0wV+GRdcoU
MXGvOGVw5WyF/vFdjpjkY7KeCgpU3BTWH3pFC2a5vUCDqgD8yndwFghJMDfSjl6d
46DIqknyveq234GK/Yz5khlbY094yL8JrJU2duva/9fGV86tgOr29xgMK28Lpyh8
AYRGO9XgmehZrEHcAQ57
=jy5l
-----END PGP SIGNATURE-----
Merge tag 'kbuild-v4.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild
Pull more Kbuild updates from Masahiro Yamada:
"Makefile changes:
- enable unused-variable warning that was wrongly disabled for clang
Kconfig changes:
- warn about blank 'help' and fix existing instances
- fix 'choice' behavior to not write out invisible symbols
- fix misc weirdness
Coccinell changes:
- fix false positive of free after managed memory alloc detection
- improve performance of NULL dereference detection"
* tag 'kbuild-v4.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (21 commits)
kconfig: remove const qualifier from sym_expand_string_value()
kconfig: add xrealloc() helper
kconfig: send error messages to stderr
kconfig: echo stdin to stdout if either is redirected
kconfig: remove check_stdin()
kconfig: remove 'config*' pattern from .gitignnore
kconfig: show '?' prompt even if no help text is available
kconfig: do not write choice values when their dependency becomes n
coccinelle: deref_null: avoid useless computation
coccinelle: devm_free: reduce false positives
kbuild: clang: disable unused variable warnings only when constant
kconfig: Warn if help text is blank
nios2: kconfig: Remove blank help text
arm: vt8500: kconfig: Remove blank help text
MIPS: kconfig: Remove blank help text
MIPS: BCM63XX: kconfig: Remove blank help text
lib/Kconfig.debug: Remove blank help text
Staging: rtl8192e: kconfig: Remove blank help text
Staging: rtl8192u: kconfig: Remove blank help text
mmc: kconfig: Remove blank help text
...
The Meson GX MMC driver fails to build after commit 23c35f48f5
("pinctrl: remove include file from <linux/device.h>") because it relies
on the pinctrl/consumer.h being pulled in by the device.h header
implicitly.
Include the header explicitly to avoid the build failure.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Blank help texts are probably either a typo, a Kconfig misunderstanding,
or some kind of half-committing to adding a help text (in which case a
TODO comment would be clearer, if the help text really can't be added
right away).
Best to remove them, IMO.
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The bounce buffer is gone from the MMC core, and now we found out
that there are some (crippled) i.MX boards out there that have broken
ADMA (cannot do scatter-gather), and also broken PIO so they must
use SDMA. Closer examination shows a less significant slowdown
also on SDMA-only capable Laptop hosts.
SDMA sets down the number of segments to one, so that each segment
gets turned into a singular request that ping-pongs to the block
layer before the next request/segment is issued.
Apparently it happens a lot that the block layer send requests
that include a lot of physically discontiguous segments. My guess
is that this phenomenon is coming from the file system.
These devices that cannot handle scatterlists in hardware can see
major benefits from a DMA-contiguous bounce buffer.
This patch accumulates those fragmented scatterlists in a physically
contiguous bounce buffer so that we can issue bigger DMA data chunks
to/from the card.
When tested with a PCI-integrated host (1217:8221) that
only supports SDMA:
0b:00.0 SD Host controller: O2 Micro, Inc. OZ600FJ0/OZ900FJ0/OZ600FJS
SD/MMC Card Reader Controller (rev 05)
This patch gave ~1Mbyte/s improved throughput on large reads and
writes when testing using iozone than without the patch.
dmesg:
sdhci-pci 0000:0b:00.0: SDHCI controller found [1217:8221] (rev 5)
mmc0 bounce up to 128 segments into one, max segment size 65536 bytes
mmc0: SDHCI controller on PCI [0000:0b:00.0] using DMA
On the i.MX SDHCI controllers on the crippled i.MX 25 and i.MX 35
the patch restores the performance to what it was before we removed
the bounce buffers.
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Benoît Thébaudeau <benoit@wsystem.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Benjamin Beckmeyer <beckmeyer.b@rittal.de>
Cc: stable@vger.kernel.org # v4.14+
Fixes: de3ee99b09 ("mmc: Delete bounce buffer handling")
Tested-by: Benjamin Beckmeyer <beckmeyer.b@rittal.de>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
specially highlighted.
First, we have converted the MMC block device from using the legacy blk
interface into using the modern blkmq interface. Not only do we get all the
nice effects from using blkmq, but it also means that new fresh nice code
replaces old rusty code. Great news to everybody that cares about MMC/SD!
It should also be noted that converting to blkmq has not been trivial, mostly
because of that we have been carrying too much of MMC specific optimizations
for the I/O request path, rather than striving to move these to the generic blk
layer. Hopefully we won't be doing that mistake, ever again.
Special thanks to Adrian Hunter (Intel) and to Linus Walleij (Linaro), who both
have been working on this for quite some time!
Second, on top of the blkmq deployment, we have enabled full support the eMMC
command queuing feature, introduced in the eMMC v.5.1 spec. This also includes
an implementation of a host driver library, supporting the corresponding CQHCI
HW. Ideally, those controllers that supports CQHCI should only need some minor
adaptations to make this play.
So far the sdhci-pci driver for the Intel GLKs and the sdhci-of-arasan driver
used on Rockchip RK3399, have enabled support for eMMC command queueing.
Worth to highlight is also that, implementing the eMMC command queuing support
has been a collaborative effort, as several people from Codeaurora, Rockchip,
Intel and Linaro have been involved. However, the work has been driven by
Adrian Hunter (Intel).
In some shadow of the above, here are the rest of the highlights:
MMC core:
- Don't remove non-removable cards during system suspend
- Add a slot-gpio helper to check capability of GPIO WP detection
MMC host:
- sdhci: Cleanups and improvements of some wakeup related code
- sdhci-pci-arasan: New variant to support Arasan PCI HW with integrated phy
- sdhci-acpi: Avoid broken UHS transfer modes on Intel CHT
- sdhci-acpi: Add support for ACPI HID of AMD Controller with HS400
- sdhci_f_sdh30: Add ACPI support
- sdhci-esdhc-imx: Enable/disable clock at runtime suspend/resume
- sdhci-of-esdhc: A few minor fixes
- mmci: Add support for new STM32 variant
- renesas_sdhi: enable R-Car D3 (r8a77995) support
- tmio/renesas_sdhi: Re-structuring, cleanups and modernizations
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJabvFuAAoJEP4mhCVzWIwp7qIQAMFyLGkmJya9woUDgPlKJZMD
pasQtW5/60ASEid4hiZsGQgDrvmq+8jba+3O6QhL/maTX69nhtQXTGvbyHlIYjIG
J8z1oaflYz3tQ2w5I+85mkDciQEECH7rIiXMwZn1WUKByptnSJaqA95b2eiB5b+/
zoCx9ZWCKeWBxuXsBf8E/Cyt7H6VndDVtIYzcmNYb8x0SdKGj8cjQ8YvtP+fIse1
5bSWzfSO33T+gHW0mxX1C9bBjSVTLB2yYyiTCdd8grUIimexatgcpj4VA1zWPNcA
EJYeXwUCULNMDobLVEd0XuScIX92ZWiKd2ITtuwh1OaLltGjubt6K6UCa3ecZfIv
RbzCTB+YpkyNGYnf+aQlbLF5OO9IWVcfMP8hTtHdcm7YbKnI2u6IFhDR4mHtFWpx
e3HZFZoIVwtBRxUwM8e2rNs0YfA96fn7+5YWqJ77pSa8rxGmIXE3Znf911MRHxej
faDoYYAFSxBlvHujQ4a/yxHRldaFGkelNCjvjnIC0+1O++im9oi3c8Agg8SYSR9H
dKckEBEXTVPz6PzXgmy5+fgNZ1UK1LLkAdVrdMBcoIY+BUi9xUBlu6Wng3Qr86Ht
YD/WO/2dLewPAx9qVnBO6L001IbS//dr+qPFjaQdkXP6F1KAKQRmrs2QngKPks2x
PQB46gFuxdLj6Ykg12wK
=kUV+
-----END PGP SIGNATURE-----
Merge tag 'mmc-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC updates from Ulf Hansson:
"There are two major achievements for MMC in this release, which
deserves to be specially highlighted.
First, we have converted the MMC block device from using the legacy
blk interface into using the modern blkmq interface. Not only do we
get all the nice effects from using blkmq, but it also means that new
fresh nice code replaces old rusty code. Great news to everybody that
cares about MMC/SD!
It should also be noted that converting to blkmq has not been trivial,
mostly because of that we have been carrying too much of MMC specific
optimizations for the I/O request path, rather than striving to move
these to the generic blk layer. Hopefully we won't be doing that
mistake, ever again.
Special thanks to Adrian Hunter (Intel) and to Linus Walleij (Linaro),
who both have been working on this for quite some time!
Second, on top of the blkmq deployment, we have enabled full support
the eMMC command queuing feature, introduced in the eMMC v.5.1 spec.
This also includes an implementation of a host driver library,
supporting the corresponding CQHCI HW. Ideally, those controllers that
supports CQHCI should only need some minor adaptations to make this
play.
So far the sdhci-pci driver for the Intel GLKs and the sdhci-of-arasan
driver used on Rockchip RK3399, have enabled support for eMMC command
queueing.
Worth to highlight is also that, implementing the eMMC command queuing
support has been a collaborative effort, as several people from
Codeaurora, Rockchip, Intel and Linaro have been involved. However,
the work has been driven by Adrian Hunter (Intel).
In some shadow of the above, here are the rest of the highlights:
MMC core:
- Don't remove non-removable cards during system suspend
- Add a slot-gpio helper to check capability of GPIO WP detection
MMC host:
- sdhci: Cleanups and improvements of some wakeup related code
- sdhci-pci-arasan: New variant to support Arasan PCI HW with integrated phy
- sdhci-acpi: Avoid broken UHS transfer modes on Intel CHT
- sdhci-acpi: Add support for ACPI HID of AMD Controller with HS400
- sdhci_f_sdh30: Add ACPI support
- sdhci-esdhc-imx: Enable/disable clock at runtime suspend/resume
- sdhci-of-esdhc: A few minor fixes
- mmci: Add support for new STM32 variant
- renesas_sdhi: enable R-Car D3 (r8a77995) support
- tmio/renesas_sdhi: Re-structuring, cleanups and modernizations"
* tag 'mmc-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (96 commits)
mmc: mmci: fix error return code in mmci_probe()
mmc: davinci: suppress error message on EPROBE_DEFER
mmc: davinci: dont' use module_platform_driver_probe()
mmc: tmio: hide unused tmio_mmc_clk_disable/tmio_mmc_clk_enable functions
mmc: mmci: Add STM32 variant
mmc: mmci: Add support for setting pad type via pinctrl
mmc: mmci: Don't pretend all variants to have OPENDRAIN bit
mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
mmc: tmio: refactor .get_ro hook
mmc: slot-gpio: add a helper to check capability of GPIO WP detection
mmc: tmio: remove dma_ops from tmio_mmc_host_probe() argument
mmc: tmio: move {tmio_}mmc_of_parse() to tmio_mmc_host_alloc()
mmc: tmio: move clk_enable/disable out of tmio_mmc_host_probe()
mmc: tmio: ioremap memory resource in tmio_mmc_host_alloc()
mmc: sh_mmcif: remove redundant initialization of 'opc'
mmc: sdhci: Rework sdhci_enable_irq_wakeups()
mmc: sdhci: Handle failure of enable_irq_wake()
mmc: sdhci: Stop exporting sdhci_enable_irq_wakeups()
mmc: sdhci-pci: Use device wakeup capability to determine MMC_PM_WAKE_SDIO_IRQ capability
...
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.
Fixes: f9bb304ce8 ("mmc: mmci: Add support for setting pad type via pinctrl")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This suppresses printing an error message during probe of the TI DaVinci
MMC driver when the error is EPROBE_DEFER.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This changes module_platform_driver_probe() to module_platform_driver()
in the TI DaVinci MMC driver.
On device tree systems, we can get a -EPROBE_DEFER when using a pinmux
for the CD GPIO, which results in the driver never loading because
module_platform_driver_probe() prevents it from being re-probed.
So, we replace module_platform_driver_probe() with
module_platform_driver() and removed the __init attributes accordingly.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
When CONFIG_PM is disabled, we get a warning about the clock handling
being unused:
drivers/mmc/host/tmio_mmc_core.c:937:13: error: 'tmio_mmc_clk_disable' defined but not used [-Werror=unused-function]
static void tmio_mmc_clk_disable(struct tmio_mmc_host *host)
^~~~~~~~~~~~~~~~~~~~
drivers/mmc/host/tmio_mmc_core.c:929:12: error: 'tmio_mmc_clk_enable' defined but not used [-Werror=unused-function]
static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
^~~~~~~~~~~~~~~~~~~
As the clock handling is now done elsewhere, this is only used when
power management is enabled. We could make the functions as __maybe_unused,
but since there is already an #ifdef section, it seems easier to move
the helpers closer to their callers.
Fixes: b21fc29438 ("mmc: tmio: move clk_enable/disable out of tmio_mmc_host_probe()")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
an ARM PL810.
This patch adds the STM32 variant so that mmci driver supports it.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
If variant hasn't the control bit to switch pads in opendrain mode,
we can achieve the same result by asking to the pinmux driver to
configure pins for us.
This patch make the mmci driver able to do this whenever needed.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This patch prepares for supporting STM32 variant which doesn't
have opendrain bit in MMCIPOWER register.
ST others variant (u300, nomadik and ux500) uses MCI_OD bit whereas
others variants uses MCI_ROD bit.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This patch prepares for supporting the STM32 variant that
has no such bit in the status register.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Two mask registers are used in order to select which events have to
actually generate an interrupt on each IRQ line.
It seems that in the single-IRQ case it's assumed that the IRQs lines
are simply OR-ed, while the two mask registers are still present. The
driver still programs the two mask registers separately.
However the STM32 variant has only one IRQ, and also has only one mask
register.
This patch prepares for STM32 variant support by making the driver using
only one mask register.
This patch also optimize the MMCIMASK1 mask usage by caching it into
host->mask1_reg which avoid to read it into mmci_irq().
Tested only on STM32 variant. RFT for variants other than STM32
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This IP provides the write protect signal level in the status
register, but it is also possible to use GPIO for WP. They are
exclusive, so it is not efficient to call mmc_gpio_get_ro() every
time from tmio_mmc_get_ro() if we know gpio_ro is not used.
Check the capability of gpio_ro just once in the probe function,
then set mmc_gpio_get_ro to .get_ro if it is the case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Like mmc_can_gpio_cd(), mmc_can_gpio_ro() will also be useful for host
drivers to know whether GPIO write-protect detection is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Drivers need to set up various struct members for tmio_mmc_host before
calling tmio_mmc_host_probe(). Do likewise for host->dma_ops instead
of passing it as a function argument.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc_of_parse() parses various DT properties and sets capability flags
accordingly. However, drivers have no chance to run platform init
code depending on such flags because mmc_of_parse() is called from
tmio_mmc_host_probe().
Move mmc_of_parse() to tmio_mmc_host_alloc() so that drivers can
handle capabilities before mmc_add_host(). Move tmio_mmc_of_parse()
likewise.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The clock is enabled in the tmio_mmc_host_probe(). It also prevents
drivers from performing platform-specific settings before mmc_add_host()
because the register access generally requires a clock.
Enable/disable the clock in drivers' probe/remove. Also, I passed
tmio_mmc_data to tmio_mmc_host_alloc() because renesas_sdhi_clk_enable()
needs it to get the private data from tmio_mmc_host.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The register region is ioremap'ed in the tmio_mmc_host_probe(), i.e.
drivers cannot get access to the hardware before mmc_add_host().
Actually, renesas_sdhi_core.c reads out the CTL_VERSION register to
complete the platform-specific settings. However, at this point,
the MMC host is already running.
Move the register ioremap to tmio_mmc_host_alloc() so that drivers
can perform platform-specific settings between tmio_mmc_host_alloc()
and tmio_mmc_host_probe().
I changed tmio_mmc_host_alloc() to return an error pointer to
propagate the return code from devm_ioremap_resource().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Variable opc is initialized with a value that is never read, opc
is later re-assigned a newer value, hence the initialization can
be removed.
Cleans up clang warning:
drivers/mmc/host/sh_mmcif.c:919:6: warning: Value stored to 'opc'
during its initialization is never read
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
In preparation for adding more conditions for whether IRQ wakeup is
enabled, rework sdhci_enable_irq_wakeups() so that needed bits are added
instead of adding them all and then removing the unneeded bits.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Now that sdhci_enable_irq_wakeups() is a local function, change it to
return whether the IRQ wakeup was successfully enabled. This is in
preparation for adding more conditions for whether IRQ wakeup is enabled.
Note it is assumed, for SDHCI devices, that suspend is more important than
wakeup, so we continue to suspend regardless.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Now that it is not being used by any drivers, stop exporting it.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
PCI and ACPI determine if a device is wakeup capable, so use that to
determine the MMC_PM_WAKE_SDIO_IRQ capability correctly.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
sdhci_enable_irq_wakeups() is already called by sdhci_suspend_host() so
sdhci-pci should not need to call it. However sdhci_suspend_host() only
calls it if wakeups are enabled, and sdhci-pci does not enable them until
after calling sdhci_suspend_host(). So move the calls to
sdhci_pci_init_wakeup() before calling sdhci_suspend_host(), and
stop calling sdhci_enable_irq_wakeups(). That results in some
simplification because sdhci_pci_suspend_host() and
__sdhci_pci_suspend_host() no longer need to be separate functions.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Add CQHCI initialization and implement CQHCI operations for Arasan
SDHCI variant host, namely arasan,sdhci-5.1, which is used by Rockchip
RK3399 platform.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Commit 5143c953a7 ("mmc: sdhci-esdhc-imx: Allow all supported
prescaler values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR
mode, thus bypassing the SD clock frequency prescaler, in order to be
able to get higher SD clock frequencies in some contexts. However, that
commit missed the fact that this value is illegal on the eSDHCv3
instance of the i.MX53. This seems to be the only exception on i.MX,
this value being legal even for the eSDHCv2 instances of the i.MX53.
Fix this issue by changing the minimum prescaler value if the i.MX53
eSDHCv3 is detected. According to the i.MX53 reference manual, if
DLLCTRL[10] can be set, then the controller is eSDHCv3, else it is
eSDHCv2.
This commit fixes the following issue, which was preventing the i.MX53
Loco (IMX53QSB) board from booting Linux 4.15.0-rc5:
[ 1.882668] mmcblk1: error -84 transferring data, sector 2048, nr 8, cmd response 0x900, card status 0xc00
[ 2.002255] mmcblk1: error -84 transferring data, sector 2050, nr 6, cmd response 0x900, card status 0xc00
[ 12.645056] mmc1: Timeout waiting for hardware interrupt.
[ 12.650473] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 12.656921] mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00001201
[ 12.663366] mmc1: sdhci: Blk size: 0x00000004 | Blk cnt: 0x00000000
[ 12.669813] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
[ 12.676258] mmc1: sdhci: Present: 0x01f8028f | Host ctl: 0x00000013
[ 12.682703] mmc1: sdhci: Power: 0x00000002 | Blk gap: 0x00000000
[ 12.689148] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000003f
[ 12.695594] mmc1: sdhci: Timeout: 0x0000008e | Int stat: 0x00000000
[ 12.702039] mmc1: sdhci: Int enab: 0x107f004b | Sig enab: 0x107f004b
[ 12.708485] mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00001201
[ 12.714930] mmc1: sdhci: Caps: 0x07eb0000 | Caps_1: 0x08100810
[ 12.721375] mmc1: sdhci: Cmd: 0x0000163a | Max curr: 0x00000000
[ 12.727821] mmc1: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x00000000
[ 12.734265] mmc1: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
[ 12.740709] mmc1: sdhci: Host ctl2: 0x00000000
[ 12.745157] mmc1: sdhci: ADMA Err: 0x00000001 | ADMA Ptr: 0xc8049200
[ 12.751601] mmc1: sdhci: ============================================
[ 12.758110] print_req_error: I/O error, dev mmcblk1, sector 2050
[ 12.764135] Buffer I/O error on dev mmcblk1p1, logical block 0, lost sync page write
[ 12.775163] EXT4-fs (mmcblk1p1): mounted filesystem without journal. Opts: (null)
[ 12.782746] VFS: Mounted root (ext4 filesystem) on device 179:9.
[ 12.789151] mmcblk1: response CRC error sending SET_BLOCK_COUNT command, card status 0x900
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Reported-by: Wladimir J. van der Laan <laanwj@gmail.com>
Tested-by: Wladimir J. van der Laan <laanwj@gmail.com>
Fixes: 5143c953a7 ("mmc: sdhci-esdhc-imx: Allow all supported prescaler values")
Cc: <stable@vger.kernel.org> # v4.13+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
To use a GPIO line for card detection, TMIO_MMC_USE_GPIO_CD is set
by a legacy board (arch/sh/boards/mach-ecovec24).
For DT platforms, the "cd-gpios" property is a legitimate way for that
in case the IP-builtin card detection can not be used for some reason.
mmc_of_parse() calls mmc_gpiod_request_cd() to set up ctx->cd_gpio if
the "cd-gpios" property is specified.
To cater to both cases, mmc_can_gpio_cd() is a correct way to check
which card detection logic is used.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
On Intel Edison the Broadcom Wi-Fi card, which is connected to SDIO,
requires 2.0v, while the host, according to Intel Merrifield TRM,
supports 1.8v supply only.
The card announces itself as
mmc2: new ultra high speed DDR50 SDIO card at address 0001
Introduce a custom OCR mask for SDIO host controller on Intel Merrifield
and add a special case to sdhci_set_power_noreg() to override 2.0v supply
by enforcing 1.8v power choice.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The inconsistent NULL checking in this function causes static checker
warnings.
drivers/mmc/host/renesas_sdhi_sys_dmac.c:360 renesas_sdhi_sys_dmac_issue_tasklet_fn()
error: we previously assumed 'host' could be null (see line 351)
On reviewing this code, "host" can't ever be NULL so we can just remove
the check.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The Fujitsu SDH30 SDHCI controller may be described as a SCX0002 ACPI
device on ACPI platforms incorporating the Socionext SynQuacer SoC.
Given that mmc_of_parse() has already been made ACPI/DT agnostic,
making the SDH30 driver ACPI capable is actually rather simple:
all we need to do is make the call to sdhci_get_of_property() [which
does not set any properties we care about] and the clock handling
dependent on whether we are dealing with a DT device, and exposing
the ACPI id via the platform_driver struct and the module metadata.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc clock can be stopped during runtime suspend and restart during runtime
resume if the sdio irq is not enabled. Stop sdio clock reduce EMI of
the device when the bus is not in use.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
runtime_resume() should re-enable the clocks in reverse order comparing with
runtime_suspend()
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
We need to return in case of error even if the actual implementation
of sdhci_runtime_suspend_host always return 0. We don't want to
power down the clock and the assuption is that the sdhci_runtime_suspend_host
always let the system consistent in case of failure
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The Arasan Controller is based on a FPGA platform and has integrated phy
with specific registers used during initialization and
management of different modes. The phy and the controller are integrated
and registers are very specific to Arasan.
Arasan being an IP provider, licenses these IPs to various companies for
integration of IP in custom SOCs. The custom SOCs define own register
map depending on how bits are tied inside the SOC for phy registers,
depending on SOC memory plan and hence will require own platform drivers.
If more details on phy registers are required, an interface document is
hosted at https://arasan.com/NF/eMMC5.1 PHY Programming in Linux.pdf.
Signed-off-by: Atul Garg <agarg@arasan.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The global array clashes with a newly added symbol of the same name:
drivers/staging/ccree/cc_debugfs.o:(.data+0x0): multiple definition of `debug_regs'
drivers/mmc/host/s3cmci.o:(.data+0x70): first defined here
We should fix both, this one addresses the s3cmci driver by removing
the symbol from the global namespace. While at it, this separates
the declaration from the type definition and makes the variable const.
Fixes: 9bdd203b4d ("s3cmci: add debugfs support for examining driver and hardware state")
Fixes: b3ec9a6736 ("staging: ccree: staging: ccree: replace sysfs by debugfs interface")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Because we started using io*_rep accessors previously because they are
more widely defined across architectures, let's be consistent and use
this family for all accessor wrappers.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
According to SD spec 3.00 3.6.1 signal voltage switch
procedure step 6~8,
(6) Set 1.8V Signal Enable in the Host Control 2 register.
(7) Wait 5ms. 1.8V voltage regulator shall be stable within this period.
(8) If 1.8V Signal Enable is cleared by Host Controller, go to step (12).
Host should wait 5ms after set 1.8V signal enable bit in
Host Control 2 register and check if 1.8V is stable or not.
But current code checks this bit right after set it.
On some platforms with xenon controller found the bit is
cleared right away and host reports "1.8V regulator output
did not became stable" and 5ms delay can help.
Implement voltage_switch callback for xenon controller to add 5ms
delay to make sure the 1.8V signal enable bit is set by controller.
Signed-off-by: Zhoujie Wu <zjwu@marvell.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Sane values for bus_shift are:
0 - for 16 bit bus
1 - for 32 bit bus
2 - for 64 bit bus
"unsigned long" is too much.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
struct tmio_mmc_host has "scc_tappos", but in fact, it is Renesas
private data. Move it to renesas_sdhi.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
struct tmio_mmc_host has "dma_dataend" and "dma_complete", but in fact,
they are Renesas private data. Move them to renesas_sdhi.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
struct tmio_mmc_dma looks like TMIO core data, but in fact, Renesas
private data. Move it to renesas_sdhi.h (probably, it is better to
rename it to renesas_sdhi_dma, or squash it into struct renesas_sdhi).
I also moved struct renesas_sdhi and host_to_priv() to that header
because they are necessary to convert the tmio_mmc_host pointer into
the renesas_sdhi pointer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
If the MMC_DRV_OP_GET_EXT_CSD request completes successfully, then
ext_csd must be freed, but in one case it was not. Fix that.
Signed-off-by: Liu Changcheng <changcheng.liu@intel.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
