Core changes:
- A new PINCTRL_GROUP_DESC() infrastructure macro is added and
used in different drivers, generic group description struct
group_desc is now used all over the place.
New drivers:
- New driver for the Texas Instruments TPS6494 Power Management IC.
- New driver for the Lantic PEF2256 framer pin multiplexer.
This IC has some pins that can be reconfigured in different
ways. The actual driver comes on an immutable branch with the
net WAN parts, the IC is some latest-and-greatest serial line
funnel for e.g. wireless access points.
- New subdriver for the Samsung Exynos Auto V920 pin controller,
used for automotive applications.
- New subdriver for the Samsung "GS101" SoC pin controller, this
is the Google "Tensor" SoC used in the Google Pixel 6.
- New subdriver for the Intel Meteor Point SoC pin controller.
- New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS pin
controllers.
- New subdriver for the Qualcomm X1E80100 top level (TLMM) pin
controller.
- New subdriver for the Qualcomm SM4450 top level (TLMM) pin
controller.
- The "single" pin controller now supports the Texas Instruments
J7200 SoC.
Improvements:
- Intel has created a new (Intel-)generic pin controller driver that
is now used by all contemporary Intel platforms.
- Intel is now also making use of some cleanup helpers.
- Enble 910 Ohm bias in the Intel Tangier driver.
- The Samsung driver now suppors irq_set_affinity() in it's IRQ chip
giving support for non wake up external gpio interrupts.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmWk3gEACgkQQRCzN7AZ
XXMfaQ/+LyuPMFxRmVj27rbw/mxs9FS6fFvnipfsQq/jTjjt4DLiPj0491UL260z
CD7T09g0rEJetWvGBbPdaxN2BE07x83E4+1d9CzszhOaIvPLnWfSPZCMRlKgHjJW
gpMAeNtRXPOQW9mny4VRoxa6QKwbE4om9WgnfsOq9SM1JfkekjcGZQGYJkGincEC
rb4efJMcaegsXo+J8nVItxp1CFV/4EbcZxaQuYwVHSGvd9WQR3aRMSnw444e9q8m
SkOxOHAPsL/y6PkolLTZFvedT7mTjKo36MuYdS6nzAuW5TgoXPfDSI38pt3s18Tg
KZb7gpqPIbbDEBd+4c93MWuOHYupNzYJnpUpCXJlDVzv0joEkQo3wnnCeoiMNjPt
sSWbnKlssKuJKBjgMS3QM7kt2Jq67v1wfm3eeBOmp+yarAMiwdGSa2jW7mScHP9M
P3pEQGFnYkwPthIM7N0SnQ0POehYHT8milOhWUtd1vEtI/hEtYVPbuh7XsBARe8P
Dj0u6iKMK1X+dqGphnzfTvnbl6elvmmKu3Qwil4bG4MFr12ptjJhGpcCTuQwBfdp
SgNJKMUKk4+4rEFwBAZQzrqiaNBifq3dcQ0DEbVMUPeQNkYSyqpflj8ROEQETf01
bnoalD2hUT0HaFgOlZswFxsQN1EESwG6X0n938VRTijuKvfrdBI=
=kj/d
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"For this kernel cycle I managed an immutable branch for the PEF2256
WAN framer that has some pin control portions. It already landed in
your tree through the net pull request but here it is mentioned again.
The most interesting is perhaps the Samsung Exynos subdrivers for the
Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for
automotive. Along with the earlier merged Tesla FSD subdriver it shows
some of the versatile uses of the Samsung Exynos silicon. It is also
used in the latest version of Axis Communications ARTPEC chips so it
is a very widely deployed SoC family.
We also have the Intel Meteor Lake SoC which I think is for laptops.
It's a pretty interesting chip with Xe graphics and integrated PCH.
Core changes:
- A new PINCTRL_GROUP_DESC() infrastructure macro is added and used
in different drivers, generic group description struct group_desc
is now used all over the place.
New drivers:
- New driver for the Texas Instruments TPS6494 Power Management IC.
- New driver for the Lantic PEF2256 framer pin multiplexer. This IC
has some pins that can be reconfigured in different ways. The
actual driver comes on an immutable branch with the net WAN parts,
the IC is some latest-and-greatest serial line funnel for e.g.
wireless access points.
- New subdriver for the Samsung Exynos Auto V920 pin controller, used
for automotive applications.
- New subdriver for the Samsung "GS101" SoC pin controller, this is
the Google "Tensor" SoC used in the Google Pixel 6.
- New subdriver for the Intel Meteor Point SoC pin controller.
- New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS
pin controllers.
- New subdriver for the Qualcomm X1E80100 top level (TLMM) pin
controller.
- New subdriver for the Qualcomm SM4450 top level (TLMM) pin
controller.
- The "single" pin controller now supports the Texas Instruments
J7200 SoC.
Improvements:
- Intel has created a new (Intel-)generic pin controller driver that
is now used by all contemporary Intel platforms.
- Intel is now also making use of some cleanup helpers.
- Enble 910 Ohm bias in the Intel Tangier driver.
- The Samsung driver now suppors irq_set_affinity() in it's IRQ chip
giving support for non wake up external gpio interrupts"
* tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: samsung: constify iomem pointers
pinctrl: cy8c95x0: Cache muxed registers
dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp
pinctrl: qcom: lpass-lpi: remove duplicated include
dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent
dt-bindings: pinctrl: qcom: drop common properties
dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings
dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom: create common LPASS LPI schema
pinctrl: qcom: sm4450: dd SM4450 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
dt-bindings: pinctrl: qcom,pmic-mpp: clean up example
pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support
pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins
pinctrl: renesas: rzg2l: Add output enable support
...
In the STMicroelectronics STM32 driver, stm32_gpio_direction_output()
ignores the result of pinctrl_gpio_direction_output() for no good reason.
Let's propagate errors from pinctrl_gpio_direction_output() upstream...
Found by Linux Verification Center (linuxtesting.org) with the Svace static
analysis tool.
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Link: https://lore.kernel.org/r/5ce023a8-db0c-13a9-be42-09e3348ca44d@omp.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The existing code does not verify if the "tentative" index exceeds
the size of the array, causing out of bound read.
Issue identified with kasan.
Check the index before using it.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Fixes: 32c170ff15 ("pinctrl: stm32: set default gpio line names using pin names")
Link: https://lore.kernel.org/r/20231107110520.4449-1-antonio.borneo@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add check for the return value of devm_kcalloc() and return the error
if it fails in order to avoid NULL pointer dereference.
Fixes: 32c170ff15 ("pinctrl: stm32: set default gpio line names using pin names")
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Acked-by: Valentin Caron <valentin.caron@foss.st.com>
Link: https://lore.kernel.org/r/20231031080807.3600656-1-nichen@iscas.ac.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl_gpio_*() helpers now have signatures corresponding with those of
the GPIOLIB callbacks. We can drop the wrappers.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that pinctrl_gpio_direction_output() is no longer used, let's drop
the '_new' suffix from its improved variant.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that pinctrl_gpio_direction_input() is no longer used, let's drop the
'_new' suffix from its improved variant.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that pinctrl_gpio_free()() is no longer used, let's drop the '_new'
suffix from its improved variant.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that pinctrl_gpio_request() is no longer used, let's drop the '_new'
suffix from its improved variant.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Replace the pinctrl helpers taking the global GPIO number as argument
with the improved variants that instead take a pointer to the GPIO chip
and the controller-relative offset.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin
descriptor which is matching with a gpio.
Most of the time pin number is equal to pin index in array. So the first
part of the function is useful to speed up.
And during gpio bank register, we set default gpio names with pin names.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20230620104349.834687-1-valentin.caron@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Make a lot of pin controllers with GPIO and irqchips immutable,
i.e. not living structs, but const structs. This is driving a
changed initiated by the irqchip maintainers.
New drivers:
- New driver for the NXP S32 SoC pin controller
- As part of a thorough cleanup and restructuring of the
Ralink/Mediatek drivers, the Ralink MIPS pin control drivers
were folded into the Mediatek directory and the family is
renamed "mtmips". The Ralink chips live on as Mediatek MIPS
family where new variants can be added. As part of this work
also the device tree bindings were reworked.
- New subdriver for the Qualcomm SM7150 SoC.
- New subdriver for the Qualcomm IPQ9574 SoC.
- New driver for the nVidia BlueField-3 SoC.
- Support for the Qualcomm PMM8654AU mixed signal circuit GPIO.
- Support for the Qualcomm PMI632 mixed signal circuit GPIO.
Improvements:
- Add some missing pins and generic cleanups on the Renesas
r8a779g0 and r8a779g0 pin controllers. Generic Renesas
extension for power source selection on several SoCs.
- Misc cleanups for the Atmel AT91 and AT91-PIO4 pin
controllers
- Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi
driver.
- Several device tree binding cleanups as the binding
YAML syntax is solidifying.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmRRcHsACgkQQRCzN7AZ
XXO8Gw/9FKVlbqYlZ8X4hi2dpNyl8Xpu+sdxHtHaBGXJqhOIzmM3N8ihx3+NPFui
lObzZ8/4CG9nt5zmKAMpPZRp4iYLRLDzaDEq8K9cVAOZz/C3UUsfXSThuvWEIrCd
1FF7qdS5r1C/R+ImJElqx9FpjShv51MzETgR24a/ycDfneB9ZQNLGK9/Om7tOUhC
OdS45XFnfwLall117ELckgVDh5fCk/UTjHI1u2Uq93f2Pdy1ZmePTqoLqXSA40uJ
rnRRueclvI/iyYZq4b/mOSwArYSd9l4wsTkba2arnlqWeJawZXXojgdp0DN3t3F/
oyJztIQPQ+jeIVXQxaXkxWx9FnLUo/xDJW7qD3l/OlCGClfPC+q6ssnwVnYwyIQb
qBYpKyP/K4UM+wVfYps6ZMyva3RN2H1/pZc/2m8IMjSz3QEOnmvkbJcL7zhgdl9m
qD/NM2gTat+7VrymENXPCDnDu2xEhUcgWnheAWTD9yc8gHQj2b6w7cJnMTZ6ep/i
3ev9A2Fo+F8t7Y8clGiL2EjNZ16xNcOgCjT9L3rRGTPin1DaKF61GPxy041yblS6
Fr5Aq5dnUWl5855mUeZrlHrR+ukA8I3bbHvhHzwMRO6xZjOsDBykOv63FaZNemOQ
BEzIlbXm49QmESsr/nPuYx2qHj2ckWWoz2BtMRV2/KgbhqKighs=
=mMr0
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Mostly drivers! Nothing special: some new Qualcomm chips as usual, and
the new NXP S32 and nVidia BlueField-3.
Core changes:
- Make a lot of pin controllers with GPIO and irqchips immutable,
i.e. not living structs, but const structs. This is driving a
changed initiated by the irqchip maintainers.
New drivers:
- New driver for the NXP S32 SoC pin controller
- As part of a thorough cleanup and restructuring of the
Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were
folded into the Mediatek directory and the family is renamed
"mtmips". The Ralink chips live on as Mediatek MIPS family where
new variants can be added. As part of this work also the device
tree bindings were reworked.
- New subdriver for the Qualcomm SM7150 SoC.
- New subdriver for the Qualcomm IPQ9574 SoC.
- New driver for the nVidia BlueField-3 SoC.
- Support for the Qualcomm PMM8654AU mixed signal circuit GPIO.
- Support for the Qualcomm PMI632 mixed signal circuit GPIO.
Improvements:
- Add some missing pins and generic cleanups on the Renesas r8a779g0
and r8a779g0 pin controllers. Generic Renesas extension for power
source selection on several SoCs.
- Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers
- Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver.
- Several device tree binding cleanups as the binding YAML syntax is
solidifying"
* tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
pinctrl-bcm2835.c: fix race condition when setting gpio dir
dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2"
dt-bindings: pinctrl: qcom: Add few missing functions
pinctrl: qcom: spmi-gpio: Add PMI632 support
dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632
pinctrl: wpcm450: select MFD_SYSCON
pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip
pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip
pinctrl: qcom spmi-mpp: Convert to immutable irq_chip
pinctrl: plgpio: Convert to immutable irq_chip
pinctrl: pistachio: Convert to immutable irq_chip
pinctrl: pic32: Convert to immutable irq_chip
pinctrl: sx150x: Convert to immutable irq_chip
pinctrl: stmfx: Convert to immutable irq_chip
pinctrl: st: Convert to immutable irq_chip
pinctrl: mcp23s08: Convert to immutable irq_chip
pinctrl: equilibrium: Convert to immutable irq_chip
pinctrl: npcm7xx: Convert to immutable irq_chip
pinctrl: armada-37xx: Convert to immutable irq_chip
pinctrl: nsp: Convert to immutable irq_chip
...
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties. As
part of this, convert of_get_property/of_find_property calls to the
recently added of_property_present() helper when we just want to test
for presence of a property and nothing more.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230310144721.1544669-1-robh@kernel.org
[Dropped hunk hitting drivers/pinctrl/renesas/pinctrl.c]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since commit 502df79b86 ("gpiolib: Warn on drivers still using static
gpiobase allocation"), one or more warnings are printed during boot on
systems where static allocation of GPIO base is used:
[ 0.197707] gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.199942] stm32f429-pinctrl soc:pinctrl@40020000: GPIOA bank added
[ 0.200711] gpio gpiochip1: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.202855] stm32f429-pinctrl soc:pinctrl@40020000: GPIOB bank added
[ 0.203591] gpio gpiochip2: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.205704] stm32f429-pinctrl soc:pinctrl@40020000: GPIOC bank added
[ 0.206338] gpio gpiochip3: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.208448] stm32f429-pinctrl soc:pinctrl@40020000: GPIOD bank added
[ 0.209182] gpio gpiochip4: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.211282] stm32f429-pinctrl soc:pinctrl@40020000: GPIOE bank added
[ 0.212094] gpio gpiochip5: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.214270] stm32f429-pinctrl soc:pinctrl@40020000: GPIOF bank added
[ 0.215005] gpio gpiochip6: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.217110] stm32f429-pinctrl soc:pinctrl@40020000: GPIOG bank added
[ 0.217845] gpio gpiochip7: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.219959] stm32f429-pinctrl soc:pinctrl@40020000: GPIOH bank added
[ 0.220602] gpio gpiochip8: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.222714] stm32f429-pinctrl soc:pinctrl@40020000: GPIOI bank added
[ 0.223483] gpio gpiochip9: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.225594] stm32f429-pinctrl soc:pinctrl@40020000: GPIOJ bank added
[ 0.226336] gpio gpiochip10: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.228490] stm32f429-pinctrl soc:pinctrl@40020000: GPIOK bank added
So let's follow the suggestion and use dynamic allocation.
Tested on STM32F429I-DISC1 board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20230227205131.2104082-1-dario.binacchi@amarulasolutions.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
of_irq_find_parent() returns a node pointer with refcount incremented,
We should use of_node_put() on it when not needed anymore.
Add missing of_node_put() to avoid refcount leak.
Fixes: d86f4d71e4 ("pinctrl: stm32: check irq controller availability at probe")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20230102082503.3944927-1-linmq006@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
In the probe path, dev_err() can be replace with dev_err_probe()
which will check if error code is -EPROBE_DEFER and prints the
error name.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220917122015.1893880-1-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
To act as an interrupt controller, a gpio bank relies on the
"interrupt-parent" of the pin controller.
When this optional "interrupt-parent" misses, do not create any IRQ domain.
This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when
the interrupt-parent = <exti> property is not declared in the Device Tree.
Fixes: 0eb9f68333 ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The np variable is used globally for stm32_pctl_probe() and in one of
its code branches. cppcheck is not happy with that:
pinctrl-stm32.c:1530:23: warning: Local variable 'np' shadows outer variable [shadowVariable]
Instead of simply renaming one of the variables convert some code to
use a device pointer directly.
Fixes: bb949ed9b1 ("pinctrl: stm32: Switch to use for_each_gpiochip_node() helper")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220507102257.26414-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When merging the for_each_gpiochip_node() changes, I made
some mistakes by not disabling the clocks on the errorpath,
fix it up.
Fixes: a091208308 ("Merge tag 'intel-gpio-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel")
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Fabien Dessenne <fabien.dessenne@foss.st.com>
Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The hardware denies any access from the Linux non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.
Mark the secure-protected GPIO lines as invalid (.init_valid_mask) and
prevent the pinmux request / pinconf setting operations.
Identify the secure pins with "NO ACCESS" in the pinconf sysfs.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220502153114.283618-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Print the name of the selected alternate function in addition to its
number. Ex:
"pin 135 (PI7): alternate 10 (SAI2_FS_A) - ..."
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20220502152524.283374-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Introduce helpers to iterate over GPIO chip nodes and covert some drivers
The following is an automated git shortlog grouped by driver:
gpiolib:
- Introduce a helper to get first GPIO controller node
- Introduce gpiochip_node_count() helper
- Introduce for_each_gpiochip_node() loop helper
pinctrl:
- meson: Replace custom code by gpiochip_node_count() call
- meson: Enable COMPILE_TEST
- meson: Rename REG_* to MESON_REG_*
- armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register()
- armada-37xx: Switch to use fwnode instead of of_node
- samsung: Switch to use for_each_gpiochip_node() helper
- samsung: Drop redundant node parameter in samsung_banks_of_node_get()
- npcm7xx: Switch to use for_each_gpiochip_node() helper
- renesas: rza1: Switch to use for_each_gpiochip_node() helper
- renesas: rza1: Replace custom code by gpiochip_node_count() call
- stm32: Switch to use for_each_gpiochip_node() helper
- stm32: Replace custom code by gpiochip_node_count() call
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQSu93Raj3rZDNXzGZv7cr9lmVa5zAUCYmwsmgAKCRD7cr9lmVa5
zEYPAP4q31AbTJHk6Fs1A79esVSo+DZSkZSzbk/n8Vr3oYG56gD/dVu5EmLNKPHU
6o5+BvdXqjHrymihHasdyD9YqI30zwM=
=MIEU
-----END PGP SIGNATURE-----
Merge tag 'intel-gpio-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel
intel-gpio for v5.19-1
* Introduce helpers to iterate over GPIO chip nodes and covert some drivers
The following is an automated git shortlog grouped by driver:
gpiolib:
- Introduce a helper to get first GPIO controller node
- Introduce gpiochip_node_count() helper
- Introduce for_each_gpiochip_node() loop helper
pinctrl:
- meson: Replace custom code by gpiochip_node_count() call
- meson: Enable COMPILE_TEST
- meson: Rename REG_* to MESON_REG_*
- armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register()
- armada-37xx: Switch to use fwnode instead of of_node
- samsung: Switch to use for_each_gpiochip_node() helper
- samsung: Drop redundant node parameter in samsung_banks_of_node_get()
- npcm7xx: Switch to use for_each_gpiochip_node() helper
- renesas: rza1: Switch to use for_each_gpiochip_node() helper
- renesas: rza1: Replace custom code by gpiochip_node_count() call
- stm32: Switch to use for_each_gpiochip_node() helper
- stm32: Replace custom code by gpiochip_node_count() call
Instead of enabling/disabling the clock at each IO configuration update,
just keep the clock enabled from the probe.
This makes things simpler and more efficient (e.g. the time required to
toggle an output IO is drastically decreased) without significantly
increasing the power consumption.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220422143608.226580-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current EOI handler for LEVEL triggered interrupts calls clk_enable(),
register IO, clk_disable(). The clock manipulation requires locking which
happens with IRQs disabled in clk_enable_lock(). Instead of turning the
clock on and off all the time, enable the clock in case LEVEL interrupt is
requested and keep the clock enabled until all LEVEL interrupts are freed.
The LEVEL interrupts are an exception on this platform and seldom used, so
this does not affect the common case.
This simplifies the LEVEL interrupt handling considerably and also fixes
the following splat found when using preempt-rt:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at kernel/locking/rtmutex.c:2040 __rt_mutex_trylock+0x37/0x62
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.109-rt65-stable-standard-00068-g6a5afc4b1217 #85
Hardware name: STM32 (Device Tree Support)
[<c010a45d>] (unwind_backtrace) from [<c010766f>] (show_stack+0xb/0xc)
[<c010766f>] (show_stack) from [<c06353ab>] (dump_stack+0x6f/0x84)
[<c06353ab>] (dump_stack) from [<c01145e3>] (__warn+0x7f/0xa4)
[<c01145e3>] (__warn) from [<c063386f>] (warn_slowpath_fmt+0x3b/0x74)
[<c063386f>] (warn_slowpath_fmt) from [<c063b43d>] (__rt_mutex_trylock+0x37/0x62)
[<c063b43d>] (__rt_mutex_trylock) from [<c063c053>] (rt_spin_trylock+0x7/0x16)
[<c063c053>] (rt_spin_trylock) from [<c036a2f3>] (clk_enable_lock+0xb/0x80)
[<c036a2f3>] (clk_enable_lock) from [<c036ba69>] (clk_core_enable_lock+0x9/0x18)
[<c036ba69>] (clk_core_enable_lock) from [<c034e9f3>] (stm32_gpio_get+0x11/0x24)
[<c034e9f3>] (stm32_gpio_get) from [<c034ef43>] (stm32_gpio_irq_trigger+0x1f/0x48)
[<c034ef43>] (stm32_gpio_irq_trigger) from [<c014aa53>] (handle_fasteoi_irq+0x71/0xa8)
[<c014aa53>] (handle_fasteoi_irq) from [<c0147111>] (generic_handle_irq+0x19/0x22)
[<c0147111>] (generic_handle_irq) from [<c014752d>] (__handle_domain_irq+0x55/0x64)
[<c014752d>] (__handle_domain_irq) from [<c0346f13>] (gic_handle_irq+0x53/0x64)
[<c0346f13>] (gic_handle_irq) from [<c0100ba5>] (__irq_svc+0x65/0xc0)
Exception stack(0xc0e01f18 to 0xc0e01f60)
1f00: 0000300c 00000000
1f20: 0000300c c010ff01 00000000 00000000 c0e00000 c0e07714 00000001 c0e01f78
1f40: c0e07758 00000000 ef7cd0ff c0e01f68 c010554b c0105542 40000033 ffffffff
[<c0100ba5>] (__irq_svc) from [<c0105542>] (arch_cpu_idle+0xc/0x1e)
[<c0105542>] (arch_cpu_idle) from [<c063be95>] (default_idle_call+0x21/0x3c)
[<c063be95>] (default_idle_call) from [<c01324f7>] (do_idle+0xe3/0x1e4)
[<c01324f7>] (do_idle) from [<c01327b3>] (cpu_startup_entry+0x13/0x14)
[<c01327b3>] (cpu_startup_entry) from [<c0a00c13>] (start_kernel+0x397/0x3d4)
[<c0a00c13>] (start_kernel) from [<00000000>] (0x0)
---[ end trace 0000000000000002 ]---
Power consumption measured on STM32MP157C DHCOM SoM is not increased or
is below noise threshold.
Fixes: 47beed513a ("pinctrl: stm32: Add level interrupt support to gpio irq chip")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Fabien Dessenne <fabien.dessenne@foss.st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
To: linux-gpio@vger.kernel.org
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220421140827.214088-1-marex@denx.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The stm32_gpio_get() should only be called for LEVEL triggered interrupts,
skip calling it for EDGE triggered interrupts altogether to avoid wasting
CPU cycles in EOI handler. On this platform, EDGE triggered interrupts are
the majority and LEVEL triggered interrupts are the exception no less, and
the CPU cycles are not abundant.
Fixes: 47beed513a ("pinctrl: stm32: Add level interrupt support to gpio irq chip")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Fabien Dessenne <fabien.dessenne@foss.st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
To: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20220415215410.498349-1-marex@denx.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Switch the code to use for_each_gpiochip_node() helper.
While at it, in order to avoid additional churn in the future,
switch to fwnode APIs where it makes sense.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Since we have generic function to count GPIO controller nodes
under a given device, there is no need to open code it. Replace
custom code by gpiochip_node_count() call.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Consider the GPIO controller offset (from "gpio-ranges") to compute the
maximum GPIO line number.
This fixes an issue where gpio-ranges uses a non-null offset.
e.g.: gpio-ranges = <&pinctrl 6 86 10>
In that case the last valid GPIO line is not 9 but 15 (6 + 10 - 1)
Cc: stable@vger.kernel.org
Fixes: 67e2996f72 ("pinctrl: stm32: fix the reported number of GPIO lines per bank")
Reported-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20211215095808.621716-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Add infrastructure for per-parent interrupt data to support
the Apple pin controller.
New drivers:
- New combined pin control and GPIO driver for the Apple SoC.
This is used in all modern Apple silicon such as the M1
laptops but also in at least recent iPhone variants.
- New subdriver for the Qualcomm SM6350
- New subdriver for the Qualcomm QCM2290
- New subdriver for the Qualcomm PM6350
- New subdriver for the Uniphier NX1
- New subdriver for the Samsung ExynosAutoV9
- New subdriver for the Mediatek MT7986
- New subdriver for the nVidia Tegra194
Improvements:
- Improve power management in the Mediatek driver.
- Improvements to the Renesas internal consistency checker.
- Convert the Rockchip pin control device tree bindings to YAML.
- Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO
driver to use hierarchical interrupts.
- Convert the Qualcomm PMIC MPP device tree bindings to YAML.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmGEimgACgkQQRCzN7AZ
XXPelQ/+M7WhOfa52zSCBMB90OrgPD1NsZnWc6+QaC96Nwh2xvf51zngt4BOdU5K
e/K85vLN8iwM9XekFRAFA5tKbm8rGXfhKMs3neuK2tQEebRJWusBAKgarYMtGAIL
dDm2i4C3LVBQDKGvjEqedctoLdVDs8mqaZFkGyrM0H6Q4cHK2jIxvtK6UImWEM4y
eKJPIJgvahKmVZoh6maMynn6b7hNs94DxLNgO+6GaSXuucJ0hJ4rqLKx/rKOW7/W
GVaxZfwSQ88zdPTSUagSXz1Q4zll32pBtcPzGPwYlsRnl/dQyWNVY0Rlon+i/Ost
DCoNkcKhrZ6qYsqlv3pqHIZvfSCWvP4krk/kJdt/ufMz2El/vO7CEMbcea2d1ZfR
rNz6upEUfvRJk3iihdjHR+KFk4AUaeGPqg/xZKkoxB7g9pk5asysiL29wuaTukwL
Av1b2hRZE7ES843rjPy88vnRi22DB0WdcHH5H7gqeOfhCoOuChZN09Al5g5aPNaP
mH8ydPXKhZZX13vZggpfKfMEltwhb5yU0diy6ECZHhV5RdTWfAzLP8cHgeiZZXJY
zXRO9z/Et9xRdWeoENmh26l3vfkr6RlfkxvA1BC8nfrYVOGyjUTnRYVlpG/QfiqQ
b4VP2NO5l/oioDp8TSK/JdY2e5VtPTJAjwQUzZU5I1kVgD+VLsk=
=4Ms6
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The most interesting aspect is that we now have initial support for
the Apple pin controller as used in the M1 laptops and the iPhones
which is a step forward for using Linux efficiently on this Apple
silicon.
Core changes:
- Add infrastructure for per-parent interrupt data to support the
Apple pin controller.
New drivers:
- New combined pin control and GPIO driver for the Apple SoC. This is
used in all modern Apple silicon such as the M1 laptops but also in
at least recent iPhone variants.
- New subdriver for the Qualcomm SM6350
- New subdriver for the Qualcomm QCM2290
- New subdriver for the Qualcomm PM6350
- New subdriver for the Uniphier NX1
- New subdriver for the Samsung ExynosAutoV9
- New subdriver for the Mediatek MT7986
- New subdriver for the nVidia Tegra194
Improvements:
- Improve power management in the Mediatek driver.
- Improvements to the Renesas internal consistency checker.
- Convert the Rockchip pin control device tree bindings to YAML.
- Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO driver to
use hierarchical interrupts.
- Convert the Qualcomm PMIC MPP device tree bindings to YAML"
* tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (55 commits)
pinctrl: add pinctrl/GPIO driver for Apple SoCs
dt-bindings: pinctrl: Add apple,npins property to apple,pinctrl
dt-bindings: pinctrl: add #interrupt-cells to apple,pinctrl
gpio: Allow per-parent interrupt data
pinctrl: tegra: Fix warnings and error
pinctrl: intel: Kconfig: Add configuration menu to Intel pin control
pinctrl: tegra: Use correct offset for pin group
pinctrl: core: fix possible memory leak in pinctrl_enable()
pinctrl: bcm2835: Allow building driver as a module
pinctrl: equilibrium: Fix function addition in multiple groups
pinctrl: tegra: Add pinmux support for Tegra194
pinctrl: tegra: include lpdr pin properties
pinctrl: mediatek: add support for MT7986 SoC
dt-bindings: pinctrl: update bindings for MT7986 SoC
pinctrl: microchip sgpio: use reset driver
dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset binding
dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells
pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip
pinctrl: qcom: spmi-mpp: hardcode IRQ counts
pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip
...
When resuming from low power, the driver attempts to restore the
configuration of some pins. This is done by a call to:
stm32_pinctrl_restore_gpio_regs(struct stm32_pinctrl *pctl, u32 pin)
where 'pin' must be a valid pin value (i.e. matching some 'groups->pin').
Fix the current implementation which uses some wrong 'pin' value.
Fixes: e2f3cf18c3 ("pinctrl: stm32: add suspend/resume management")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20211008122517.617633-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the 'st,package' property is optional, outputting the "No package
detected" warning-level log when the property is absent is unsuitable.
Remove that log.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20211008122454.617556-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO
banks contain same features as STM32MP157 GPIO banks except that
each GPIO line of the STM32MP135 can be secured.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de
Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- Last merge window we created a driver for the Ralink RT2880.
We are now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.
- Qualcomm SM6125 SoC pin control driver.
- Qualcomm spmi-gpio support for PM7325.
- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
- Mediatek MT8365 SoC pin controller.
- New device HID for the AMD GPIO controller.
Improvements:
- Pin bias config support for a slew of Renesas pin controllers.
- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.
- Implement irq_set_wake on the AMD pin controller so we can wake
up from external pin events.
Misc:
- Devicetree bindings for the Apple M1 pin controller, we will probably
see a proper driver for this soon as well.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmDeTu0ACgkQQRCzN7AZ
XXO2Yg/+LHbqYX8V+Ig1ZcY4p5bfbGyyC6QG6g3d/kzzCmsjHFgmDFQoZ+LoRx+p
FRUSvmiR0VERMZCEepHsZgzns6ezzJfBt4Cu/388d4iYZppaETpQV47TzqY3eP7Q
4Shu2wIKwd7C3vNrCifub0JOYAAEsqdlHd75g0bqhal9hgH/MgYQSq9F22/TKAFl
hteFwyw5L4OwKIDUpqDOIcG8thhHYWrQy77/Pp82/TVnmO9gamt863dKBjIg6iF9
c+pmIWI8K2mBhNO+epGG4VSroUudIBwKV88nwUjKSe+pu0VAU7lit/V0Uh1IhG0s
FUHHGDeF62Ncn4SOYetlnSlKbQkhJaBDV2sDgQ3xzqvs1P3WEHRWqYIh1egq5iW6
/KtpSlRLQ/aO+k0iN66pErpAfsGNFAxkqlCSypyJG7ROnb2rADzZ0ftEKQb8RzZb
nypPupOO5/bFfQHbQtFORDaNu9MUTR5PR04eTPMoApG0nv7zY+kcJ6iJuKE9spLb
ahoxLstfQ/fKK27yms72E6PqwanuUEzcQv7gjhuHmFEjNrW1ARUqoa5hpdAzhZOX
20P8SZWkSeUZnqB26YQq+1U9p6wV0064Vp+jYY/wzQpV40dgX9oumiRkxCWCzpjt
6mw6x9txlrEEu+2WadW8yZd4ewKvWFLEGI+C/83pnI5NF1Dp0Go=
=Ajcr
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.14 kernel. Not so
much going on. No core changes, just drivers.
The most interesting would be that MIPS Ralink is migrating to pin
control and we have some bindings but not yet code for the Apple M1
pin controller.
New drivers:
- Last merge window we created a driver for the Ralink RT2880. We are
now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.
- Qualcomm SM6125 SoC pin control driver.
- Qualcomm spmi-gpio support for PM7325.
- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
- Mediatek MT8365 SoC pin controller.
- New device HID for the AMD GPIO controller.
Improvements:
- Pin bias config support for a slew of Renesas pin controllers.
- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.
- Implement irq_set_wake on the AMD pin controller so we can wake up
from external pin events.
Misc:
- Devicetree bindings for the Apple M1 pin controller, we will
probably see a proper driver for this soon as well"
* tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits)
pinctrl: ralink: rt305x: add missing include
pinctrl: stm32: check for IRQ MUX validity during alloc()
pinctrl: zynqmp: some code cleanups
drivers: qcom: pinctrl: Add pinctrl driver for sm6125
dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver
dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios
pinctrl: mcp23s08: Add optional reset GPIO
pinctrl: mediatek: fix mode encoding
pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
pinctrl: bcm: Constify static pinmux_ops
pinctrl: bcm: Constify static pinctrl_ops
pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
pinctrl: ralink: move ralink architecture pinmux header into the driver
pinctrl: single: config: enable the pin's input
pinctrl: mtk: Fix mt8365 Kconfig dependency
pinctrl: mcp23s08: fix race condition in irq handler
...
Considering the following irq_domain_ops call chain:
- .alloc() is called when a clients calls platform_get_irq() or
gpiod_to_irq()
- .activate() is called next, when the clients calls
request_threaded_irq()
Check for the IRQ MUX conflict during the first stage (alloc instead of
activate). This avoids to provide the client with an IRQ that can't be
used.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Each GPIO bank supports a variable number of lines which is usually 16, but
is less in some cases : this is specified by the last argument of the
"gpio-ranges" bank node property.
Report to the framework, the actual number of lines, so the libgpiod
gpioinfo command lists the actually existing GPIO lines.
Fixes: 1dc9d28915 ("pinctrl: stm32: add possibility to use gpio-ranges to declare bank range")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144629.2557693-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "invalid function %d on pin %d .\n" message is triplicated in the
driver in different variants, just pull it into the function and have
it once in the driver. The bonus is that all variants of the message
now print the pin number and AF consistently, so it is easier to debug
such pinmux problems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabien Dessenne <fabien.dessenne@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Acked-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210406180035.279249-1-marex@denx.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix OF node leaks by calling of_node_put in
for_each_available_child_of_node when the cycle returns.
Generated by: scripts/coccinelle/iterators/for_each_child.cocci
Signed-off-by: Junlin Yang <yangjunlin@yulong.com>
Link: https://lore.kernel.org/r/20210215103643.898-1-angkery@163.com
Acked-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the hwspin_lock_timeout_in_atomic() API which is the most appropriated
here. Indeed:
- hwspin_lock_() is called after spin_lock_irqsave()
- the hwspin_lock_timeout() API relies on jiffies count which won't work
if IRQs are disabled which is the case here.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615124456.27328-1-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adds the possibility to configure a single pin through the gpiolib (i.e:
to set PULL_UP/PULL_DOWN config).
Mutex behavior is slightly changed to avoid a deadlock when pin_config_set
is called (in this case pctldev->mutex is already taken).
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125951.28008-3-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
".pin_config_set" or ".pin_config_group_set" can be called with a
configuration not supported (i.e. PIN_CONFIG_PERSIST_STATE). In this case,
it is more suitable to return -ENOTSUPP instead of -EINVAL.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125951.28008-2-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Defer probe when pin controller reset is defined in the system resources
but not yet probed.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125407.27632-3-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change STM32 pinctrl driver to not print an error trace when probe is
deferred due to clock resource. Probe defer issue (for clocks) could
occur during bank registering when some banks have already been registered.
In this case banks already registered should be released. To not waste time
in this case, it is better to check first if all clocks are available
before registering banks.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125407.27632-2-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are no core changes this time, only driver developments.
- New driver for the Dialog Semiconductor DA9062 Power Management
Integrated Circuit (PMIC).
- Renesas SH-PFC has improved consistency, with group and
register checks in the configuration checker.
- New subdriver for the Qualcomm IPQ6018.
- Add the RGMII pin control functionality to Qualcomm IPQ8064.
- Performance and code quality cleanups in the Mediatek
driver.
- Improve the Broadcom BCM2835 support to cover all the GPIOs
that exist in it.
- The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
suspend.
- Add some missing groups and functions to the Ingenic driver.
- Convert some of the Freescale device tree bindings to use the
new and all improved JSON YAML markup.
- Refactorings and support for the SFIO/GPIO in the Tegra194
SoC driver.
- Support high impedance mode in the Spreadtrum/Unisoc driver.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl6FlRoACgkQQRCzN7AZ
XXPiAxAAuAvY07H739YF4ANvtLpfbtz0KBK4M2XGiD41VMcp5MhZtT9TdXAIRisb
W4QMHbMxhwO4gdxmhVOetXeQNQnHch4oPsFyd1UdyuwNEtvlm8qst99VcdQPz7Jv
zyL4cat1fTrwdcnLQl5eaJR7a9bKLqAd4rlb/suQZsaVf+URUWJyZBuU41GEx9A+
w+EPv8doxTWRaE0NpafIwNCLxTR3i2Vt59fkRT4pSi8fTu9/Zv5yW8yWvbYZdlaO
2bUaFjN65oyiikjPTgyQxb95A8yDJHkNnkgfTw4ghCY/k8u3GvMfKS7V1tO+nq6B
bkv9E3jR1u7Ktkq1rLshS2eycl02uSJ3OmzyfL8S/GQxVdUPi3+X3hmyv2ctbEvC
qy+7F6zx/Pt/WdPnAisdsVai9T3/YGoSN1C3n7Ufltjcrt0w5xP7/AgEVR4nHHMP
NMWNoauGWsBDKtYPG7beX3thjkm3mUpezcEOxho7+r5tOtBaU623pWr+NHEPZu48
8oKOCILaUkacUmmMjjOzraAeOxV7Ut+xumu0mgMj0EjZfJZDrgQsqkmfMbGcU5Fa
y4S5+tAd+cELXveLVJB3Ml9u1R037x8VtAv+Z2a7qVnf1gSgf0bpAJ+SnfC/XbLX
fBpSCsIMXSpioVNuS9gbkpnfsRPcTOrOXyxinP5onI8AHlIj1Rg=
=1ZKq
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.7 kernel cycle.
There are no core changes this time, only driver developments:
- New driver for the Dialog Semiconductor DA9062 Power Management
Integrated Circuit (PMIC).
- Renesas SH-PFC has improved consistency, with group and register
checks in the configuration checker.
- New subdriver for the Qualcomm IPQ6018.
- Add the RGMII pin control functionality to Qualcomm IPQ8064.
- Performance and code quality cleanups in the Mediatek driver.
- Improve the Broadcom BCM2835 support to cover all the GPIOs that
exist in it.
- The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
suspend.
- Add some missing groups and functions to the Ingenic driver.
- Convert some of the Freescale device tree bindings to use the new
and all improved JSON YAML markup.
- Refactorings and support for the SFIO/GPIO in the Tegra194 SoC
driver.
- Support high impedance mode in the Spreadtrum/Unisoc driver"
* tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits)
pinctrl: qcom: fix compilation error
pinctrl: qcom: use scm_call to route GPIO irq to Apps
pinctrl: sprd: Add pin high impedance mode support
pinctrl: sprd: Use the correct pin output configuration
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
pinctrl: tegra: Renumber the GG.0 and GG.1 pins
pinctrl: tegra: Do not add default pin range on Tegra194
pinctrl: tegra: Pass struct tegra_pmx for pin range check
pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
pinctrl: tegra: Fix whitespace issues for improved readability
pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow
pinctrl: freescale: drop the dependency on ARM64 for i.MX8M
Revert "pinctrl: mvebu: armada-37xx: use use platform api"
dt-bindings: pinctrl: at91: Fix a typo ("descibe")
pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm
pinctrl: sprd: Fix the kconfig warning
pinctrl: ingenic: add hdmi-ddc pin control group
pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member
pinctrl: sprd: Allow the SPRD pinctrl driver building into a module
pinctrl: Export some needed symbols at module load time
...
Sampling the IRQ line state in EOI and retriggering the interrupt to
work around missing level-triggered interrupt support only works for
non-threaded interrupts. Threaded interrupts must be retriggered the
same way in unmask callback.
Signed-off-by: Marek Vasut <marex@denx.de>
[maz: fixed missing static attribute]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200323235132.530550-1-marex@denx.de
GPIO hardware block is directly linked to EXTI block but EXTI handles
external interrupts only on edge. To be able to handle GPIO interrupt on
level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip)
is retriggered following interrupt type and gpio line value.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marek Vasut <marex@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200219143229.18084-3-alexandre.torgue@st.com
Use newly added GPIO defines GPIO_LINE_DIRECTION_IN and
GPIO_LINE_DIRECTION_OUT instead of using hard-coded 1 and 0.
Main benefit is to make it easier to see which values mean IN and which
OUT. As a side effect this helps GPIO framework to change the direction
defines to something else if ever needed.
Please note that return value from get_direction call on
pinctrl-axp209 driver was changed. Previously pinctrl-axp209 might have
returned value 2 for direction INPUT.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reported-by: kbuild test robot <lkp@intel.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20200214135712.GA14557@localhost.localdomain
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
