3 commits

Author	SHA1	Message	Date
Conor Dooley	2a5303b499	Documentation: riscv: fix insufficient list item indent ... When adding the ISA string ordering rules, I didn't sufficiently indent one of the list items. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/linux-doc/202301300743.bp7Dpazv-lkp@intel.com/ Fixes: f07b2b3f9d ("Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20230129235701.2393241-1-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2023-02-14 16:00:02 -08:00
Conor Dooley	f07b2b3f9d	Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo ... The RISC-V specs are permissive in what they allow as the ISA string, but how we output this to userspace in /proc/cpuinfo is quasi uABI. Formalise this as part of the uABI, by documenting the list of rules we use at this point in time. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221205144525.2148448-4-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2023-01-17 22:05:33 -08:00
Palmer Dabbelt	06267eb2de	doc: RISC-V: Document that misaligned accesses are supported ... The RISC-V ISA manual used to mandate that misaligned accesses were supported in user mode, but that requirement was removed in 2018 via riscv-isa-manual commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture."). Since the Linux uABI was already frozen at that point it's just been demoted to part of the uABI, but that was never written down. Link: https://lore.kernel.org/r/20220728210715.17214-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2022-10-12 08:58:10 -07:00