NXP LPC32xx SoC has one USB OTG controller, which is supposed to work
with an external phy (default is NXP ISP1301).
Practically the USB controller contains 5 subdevices:
- host controller 0x3102 0000 -- 0x3102 00FF
- OTG controller 0x3102 0100 -- 0x3102 01FF
- device controller 0x3102 0200 -- 0x3102 02FF
- I2C controller 0x3102 0300 -- 0x3102 03FF
- clock controller 0x3102 0F00 -- 0x3102 0FFF
The USB controller can be considered as a "bus", because the
subdevices above are relatively independent, for example I2C
controller is the same as other two general purpose I2C controllers
found on SoC.
The change is not intended to modify any logic, but it rearranges
existing device nodes, in future it is planned to add a USB clock
controller device node into the same group.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
In case if SDRAM memory region is not populated by a bootloader,
provide this value in device trees for EA3250 and PHY3250 boards.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change replaces /include/ to #include in lpc32xx.dtsi and
derivatives, it is required, if C preprocessor is intended to be used
over dtsi/dts files, otherwise errors like one below are generated:
Error: ea3250.dts:15.1-9 syntax error
FATAL ERROR: Unable to parse input tree
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
There is another reference/development board for the LPC32xx SoC (besides the
Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts
file for it.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
