Device tree files included here haven't got SPDX license header at all.
Hence, add it to all of them.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20211025094240.4356-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Hexadecimal addresses in device tree must be defined using lower case.
Change missing one in 'gbpc1.dts' file.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20211019102915.15409-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pcie node is being overlayed in 'gbpc1.dts' file requesting three
gpio reset pins for each pcie port. Gnubee only needs general
gpio 19 to properly reset and make all of them work. This pin
is already requested in the general 'mt7621.dtsi' file as well
as is the pinctrl pins. So we only need to enable the node
in the overlay and all the other stuff can be safely deleted.
Also, pin 8 is being requested for gpio-leds node and there
was an error on boot before this changes because of pin was
already assigned (EBUSY):
leds-gpio: probe of gpio-leds failed with error -16
With this changes this error has disappear and the board is
properly booting without any other regression.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604063031.13599-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210410055059.13518-3-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There are three pins that can be used for reset gpios.
As mentioned in the application note, there are two
possible way of wiring pcie reset:
* connect gpio19 to all pcie reset pins
* connect gpio19 to pcie0 reset and pick two other
gpios for pcie1 and pcie2
gpio7 and gpio8 may not be used as pcie reset and are
vendor specific. Hence, maintain common mt7621.dtsi with
only gpio19 which is common and make an overlay for gnubee
board which uses all gpio's as resets for pcie. After this
changes release gpios in driver code is not needed anymore.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200321072650.7784-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The mt7621 has two network interfaces, one that connects to an
internal switch, and one that can connect to either that switch
or an external phy, or possibly an internal phy.
The Gnubee-PC2 has an external phy for use with the second interface.
This patch add some support for the second interface to mt7621.dtsi
and add a gbpc2.dts which makes use of this. This allows the second
interface to be used.
I don't fully understand how to configure this interface - the
documentation is thin - so there could well be room for improvement
here.
Signed-off-by: NeilBrown <neil@brown.name>
Link: https://lore.kernel.org/r/156194178766.1430.12784163026696670896.stgit@noble.brown
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The ethernet in mt7621 is now supported by
drivers/net/ethernet/mediatek/
which provides support for the integrated switch through DSA.
This requires some devicetree changes, and particularly allows
a board dts to identify which switch ports are present.
The second CPU interface - gmac1 - doesn't work yet, so the device
tree information may not be correct. The phy (which is present on the
gnubee-pc2) can negotiate and report connection speed etc, but no
traffic flows.
The gnubee-pc1 has two network ports which are 'black' and 'blue'.
There are connected to switch ports 0 and 4 respectively.
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Pinctrl generic functions looks for standard property 'groups' in DT to get
data and use in the driver. Change all of them.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Since commit bb276262e8 ("mtd: spi-nor: only apply reset hacks to
broken hardware"), we need to mark the spi-nor as "broken" for reboot
to work.
Note that nothing is actually broken here. The hardware-watchdog in
the SoC isn't wired in a way that works, but then the board doesn't
claim to support a hardware watchdog - and the SPI certain isn't
"broken".
This causes an annoying warning on every boot, but that is better than
failing on ever reboot.
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Banks shouldn't be defined in DT if number of resources
per bank is not variable. We actually know that this SoC
has three banks so take that into account in order to don't
overspecify the device tree. Device tree will only have one
node making it simple. Update device tree, binding doc and
code accordly.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This currently fixes the remaining dtb warnings:
Node /pcie@1e140000/pcie0 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie1 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie2 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie0 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie0 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie0 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie1 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie1 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie1 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie2 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie2 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie2 missing bus-range for PCI bridge
Warning (unit_address_format): Failed prerequisite 'pci_bridge'
Warning (pci_device_reg): Failed prerequisite 'pci_bridge'
Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
device_type was removed since according to documentation, it's deprecated
for pci(e) devices.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Now that gpio-interrupts work correctly, we
can use gpio-keys instead of gpio-keys-polled
for the single push-button on the gbpc-1.
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The MT7621 documentation says that the sys clock - also known
as OCP clock for the Open Core Protocol - can be configured to
1/3 or 1/4 of the CPU clock.
Testing on my hardware, using the fact that the SPI clock is
based on the OCP clock and measuring transfer rates, shows
a clock of a little over 200MHz with a CPU clock of 900MHz.
So assume 1/4 is the default.
Also, the nor-flash in the gbpc1 is documented as accepting 50MHz
for request requests, and higher for other requests. So set
maximum to 50MHz.
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The GNUBEE has 32MB flash, so set partitions accordingly.
Also remove "m25p,chunked-io" which isn't documented or
used anywhere (outside of freewrt).
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add device tree source for mt7621 and gnubee1 to
make testing easier.
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Sergio Paracuellos