The core addition is the support for the rk3399-based Gru family of
ChromeOS devices, like the Kevin board which is the recently released
Samsung Chromebook Plus. Additionally the usb3 controllers are added
to rk3399 as they're used on Gru devices and even without full type-c
support they can at least drive usb2 devices already.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY62IQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYkKCACdlgqbhUPiGj/xGqSlBRdWzX20nMAmFMLh
jPDSX3wjOTtmxCUoyGB4eac/823fVydVzf0OeLGTyJc7zx3IS+7p6dPMdV0ulLio
UAKyhJk6HbAOWdQXRZFQbSGeWfcaRB12gu5uNbUiwaDsD7Pguk2z/H/z9pS03ydB
OIXB3UrIKl0YW0CYhqH6Rt09af/8q3IaTDVwJpAXvAUNVcYogUK797fTXsxH8CD2
e92qmtbEEdI6FGsACP6OTQx2mBDZCd+weABaacxKhIJ9IPce8QHVtcZj2VjH43L7
TzIZkQ4b5MMG176mpofNzv2+O3i9BAzAkoX87czz7Y9fwuf7pFfy
=rqs0
-----END PGP SIGNATURE-----
Merge tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 updates (using arm/arm64 symlinks) for 4.12 part1" from Heiko Stübner
Rockchip dts changes based on the newly created arm/arm64 symlinks.
The core addition is the support for the rk3399-based Gru family of
ChromeOS devices, like the Kevin board which is the recently released
Samsung Chromebook Plus. Additionally the usb3 controllers are added
to rk3399 as they're used on Gru devices and even without full type-c
support they can at least drive usb2 devices already.
* tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add regulator info for Kevin digitizer
arm64: dts: rockchip: describe Gru/Kevin OPPs + CPU regulators
arm64: dts: rockchip: add Gru/Kevin DTS
dt-bindings: Document rk3399 Gru/Kevin
arm64: dts: rockchip: support dwc3 USB for rk3399
default, mmc-resets) and also removes the wrongly added idle states, that
do not match the hardware's capabilities, as well as some general rk3399
pcie fixes as well as also the mmc resets.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY6c0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgdIYB/wKt/kONmWhi3RsXCXFUv/PBM0NToKvUq5e
5LvprMvIb/dyEBpA1bSaxOmktYDmEzqQFfxBOT7gfWX8/N+oFLWsfLsMNGkReev0
QPxQaITA1sOVSqDPWb5Pw4jDJ58CKUH1Cvj9GU1NuU3qp5ioggMTr/RFk2FsQ2wi
AJTDmyRHIp2Hfr7C//H85U7qd0NB0xQJz4GpZ98HnuZoSzpeQs7SRikOr4PZAaEA
mqsFizsELiAee/BmsTsppjzEIM5MpCIe91fx4S5NBNbnbmy2pFvXsmL5QazTWyao
FiWPPcIWuEVnuVLWXAGn4vLlKJG7DH+aJSOtN482J/fRnaTZABU6
=/nLm
-----END PGP SIGNATURE-----
Merge tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 updates for 4.12 part1" from Heiko Stübner:
Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that
do not match the hardware's capabilities, as well as some general rk3399
pcie fixes as well as also the mmc resets.
* tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix PCIe domain number for rk3399
arm64: dts: rockchip: add rk3399 dw-mmc resets
arm64: dts: rockchip: add rk3368 dw-mmc resets
arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default
arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
arm64: dts: rockchip: add dmac nodes for rk3368 SoCs
arm64: dts: rockchip: remove wrongly added idle states on rk3368
arm64: dts: rockchip: sort rk3399-pcie by unit address
4.12, please pull the following:
- Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
Device Tree nodes
- Jon replaces all occurences of: status = "ok" with status = "okay" to better
conform to the Device Tree specification
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY1VaOAAoJEIfQlpxEBwcEcV4P/3jbaahcHY8RQgzUEV2IOHL6
r82SI54BGNzrLRZQCeOQopUzTSiVtpSuFkjaZZr3zsKg0rFOQL5krQQiqXFq4m4G
uzzBRCFXJb4ePE/czylE6YyNZFjAiQmpvWltNJwRQ8vbEml5M3B/PEfWaW9OTFxx
5FulbvF1RG4zU0BG3DS1YggejQqNmNiT/CvwVBg1qLq2m9yGXd8XVsIRKMVxKGTx
YZnxAEKueE/DqY5N9WvwKcTPP7JzBPPSPLqbSlPFI5+uRKn/EQ6pHBbSzCQXGEjb
hpfKkMK2gFhnNw0Uvb9k5cT/sbst3evsaYGTE6q2DplKchCF1D1OQbUK5Dqn2ork
MvitS7zkOavHrx+QPP0QkwPjWJrcCNnlIGwjFR/L8xl1Cz0WvSg9npyLVJr5kjmH
uLDnx1RxKzDDaf/K42ZmuABRC7OURf2w7ARoAD4Z8Y4hRe+in7A9YTP8pHMjOcgG
BR1aSr6zgLnqvMJDT+p0WrCTiEnd4rOJKL2zM/mmYdlYzkLe+HQ1YTi3mkCkEaTR
Ao6TH8uAGJnc5ve7xY50ChNDlbKOUL6Nip/RMiayqr6JfG5OkMoqkrhF9gLYcnNo
c4zLRT7sKBXJrYHqgo3xZuk41mYaiqoSsYiuXS283T1miOK1BWZ0ZzqIP+MH53yz
yA1EmWP1XdHuU6hvKrZ8
=yeV5
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom devicetree-arm64 changes for 4.12" from Florian Fainelli:
This pull request contains Broadcom ARM64-based SoCs Device Tree updates for
4.12, please pull the following:
- Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
Device Tree nodes
- Jon replaces all occurences of: status = "ok" with status = "okay" to better
conform to the Device Tree specification
* tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: convert "ok" to "okay"
arm64: dts: NS2: Add Broadcom SPU driver DT entry
- Add RTC support on Armada 7k/8k
- Improve i2c support on Armada 37xx
- Add gpio expander and RTC on Armada 3720 board
- Improve USB3 support on Armada 37xx
- Add network support on Armada 7k/8k
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWNVViCMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71b/NAJ9Y60FsHOFK
08mr2r3h/4+ydzlxWQCfQeR509BowT9/i92+Rl1ZhqS7SS0=
=kbjv
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.12 (part 1)" from Gregory CLEMENT:
- Add RTC support on Armada 7k/8k
- Improve i2c support on Armada 37xx
- Add gpio expander and RTC on Armada 3720 board
- Improve USB3 support on Armada 37xx
- Add network support on Armada 7k/8k
* tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
ARM64: dts: marvell: armada-3720 add RTC support
ARM64: dts: marvell: armada-3720-db: Add phy for USB3
ARM64: dts: marvell: armada-37xx: Add clock resource for USB3
ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3
ARM64: dts: marvell: armada-3720-db: add gpio expander
ARM64: dts: marvell: armada37xx: add address and size property for i2c cells
arm64: dts: marvell: add RTC description for Armada 7K/8K
Move and update device tree files as part of transition from Broadcom
Vulcan to Cavium ThunderX2.
The changes are to:
* rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi,
update cpu cores to be "cavium,thunder2", and update SoC to be
"cavium,thunderx2-cn9900"
* move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi
and update board name string
* Update dts/broadcom/Makefile not to build vulcan dtbs
* Update dts/cavium/Makefile to build thunder2 dtbs
No changes to the dts contents except the updated "compatible" and
"model" properties.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 3720 DB board has an RTC on the I2C bus. It's a PT7C4337A from
Pericom but which claims to be fully compatible with the ds1337.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Now that the gpio expander is present in the dts, use it to add an USB3
PHY using one of these gpio as a regulator.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
We need to enable this regulator before the digitizer can be used. Wacom
recommended waiting for 100 ms before talking to the HID.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[store chip ident as comment until i2c multi-compatibles are sorted]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
It's suggested to fix the domain number for all PCIe
host bridges or not set it at all. However, if we don't
fix it, the domain number will keep increasing ever when
doing unbind/bind test, which makes the bus tree of lspci
introduce pointless domain hierarchy. More investigation shows
the domain number allocater of PCI doesn't consider the conflict
of domain number if we have more than one PCIe port belonging to
different domains. So once unbinding/binding one of them and keep
others would going to overflow the domain number so that finally
it will share the same domain as others, but actually it shouldn't.
We should fix the domain number for PCIe or invent new indexing
ID mechanisms. However it isn't worth inventing new indexing ID
mechanisms personlly, Just look at how other Root Complex drivers
did, for instance, broadcom and qualcomm, it seems fixing the domain
number was more popular. So this patch gonna fix the domain number
of PCIe for rk3399.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3399.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3368.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add dmac bus and dmac peri dts nodes for peripherals,
such as I2S, SPI, UART and so on.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As reported by Lorenzo, the residency/latency values defined in the
idle-state for rk3368 "make no sense". When introducing them I
simply took the idle-state node from the vendor kernel in error
as I didn't look up if these values were sane in the first place.
Talking to people and determining why they were used in this way
showed that it was meant to make sure the cpu_suspend callback
got initialized which at the 3.10 time was somehow required even
for wfi-based idle handling.
Of course the generic arch_cpu_idle() now does wfi-based idle-handling
already and the rk3368 does not implement any other idle states than
the default WFI, so these wrong idle-states should go away.
Reported-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Used for Gru/Kevin only, as they're the only ones which have a described
CPU regulator. Also, I'm not sure we've validated this table non-Gru
boards.
At the same time, partially describe PWM regulators for Gru, so cpufreq
doesn't think it can crank up the clock speed without changing the
voltage. However, we don't yet have the DT bindings to fully describe
the Over Voltage Protection (OVP) circuits on these boards. Without that
description, we might end up changing the voltage too much, too fast.
Add the pwm-regulator descriptions and associate the CPU OPPs, but leave
them disabled.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[shared gru/kevin parts on a gru device]
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[with a bit of reordering]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Kevin is part of a family of boards called Gru. As best as possible, the
properties shared by the Gru family are placed in rk3399-gru.dtsi, while
Kevin-specific bits are in rk3399-gru-kevin.dts. This does not add full
support for the base Gru board.
Working and tested (to some extent):
* EC support -- including keyboard, battery, PWM, and probably more
* UART / console
* Thermal
* Touchscreen
* Touchpad
* Digitizer (regulator still WIP)
* PCIe / Wifi
* Bluetooth / Webcam
* SD card
* eMMC
* USB2 on TypeC
- This works much of the time, but USB3 devices may or may not detect
properly. Waiting on proper extcon support for USB3 over TypeC.
- Depends on XHCI/DWC3 fixes for ARM64 that still haven't landed
* Backlight
Not working:
* CPUFreq -- relies on special OVP support for our PWM regulator
circuits
* EC / extcon support -- and with it, USB3/TypeC/DP
* DRM -- won't even build on ARM64, so all display, eDP, etc. is not
enabled
Not tested:
* Audio
Signed-off-by: Brian Norris <briannorris@chromium.org>
[shared gru/kevin parts on a gru device]
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[with a bit of reordering]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the dwc3 usb needed node information for rk3399.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cleanup:
* Drop superfluous status update for frequency override from all
r8a779[56] boards
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs
Enhancements:
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
* Add Cortex-A53 CPU cores to r8a7795 SoC
* Update memory node to 4 GiB map on h3ulcb board
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
* Set drive-strength for ravb pins for r8a7795/salvator-x board
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
* Enable I2C for DVFS device r8a779[56]/salvator-x boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYz5gjAAoJENfPZGlqN0++SekP/0Po++ReWK9zraXuEnCKROwN
kz/iVv+uuY+RrClouw1SVO5NgMn5guQeSOWPouslJIa/+rr7tOQFJDiTEBUd2h2Z
ekZDQhrAPTK5vZdIQ/RFPVxda4auGHkOkZJ14GjbyA4gOMCTeXw89HNe30R4/IYk
D3RItR7ZTljiGZ1TdqI72XR0s8NIWpt2Jo/0e8mpUZXggJbJXfdIOUzoiurMkQfx
NADqARx2KzevaSJig1jIEkgJBseciiuiexgNbQIhrwecW12cECu0bhVuxLjxHnns
YsZajCvDXprVwc1v+goq7qi5612owUMmYJ3awo50cg+iI8t/OC40Y+pwrIGrPU7c
m5bV4RzMkoY71M8p/z08S8J6djrg4DfIX8GASvmaCgY8Y9hs4j+6rPRm324V30+S
dYKFCSigRonfk21Y3low3xPC+lUTbL78zeGc739YPSVoe80u33kds9NLmTzsmaZ4
0igqNJU8xGQCt8eVLDQyRE8M6ZzBd2+Vl+85SXmMgOLXajyhsg4owLEs4oftmLK3
UGBZlyktUrmNSaAgJ+4S4thLkOSAmjJYgavmURhb95GTKWTgAlZvvMFt5attMG3H
6Xf/5MldlgsNm2KqsuZiVEcWg19Sp2Yp2otHyjDnKqMZUGfj9F4EsGu8ExYCo9/W
l0EV+sTS5fAro7TgRqyQ
=LynK
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.12
Cleanup:
* Drop superfluous status update for frequency override from all
r8a779[56] boards
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs
Enhancements:
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
* Add Cortex-A53 CPU cores to r8a7795 SoC
* Update memory node to 4 GiB map on h3ulcb board
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
* Set drive-strength for ravb pins for r8a7795/salvator-x board
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
* Enable I2C for DVFS device r8a779[56]/salvator-x boards
* tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override
arm64: dts: m3ulcb: Drop superfluous status update for frequency override
arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides
arm64: dts: h3ulcb: Drop superfluous status update for frequency override
arm64: dts: r8a7796: Add Cortex-A53 PMU node
arm64: dts: r8a7796: Add Cortex-A53 CPU cores
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
arm64: dts: r8a7796: Add Cortex-A57 PMU node
arm64: dts: r8a7796: Add Cortex-A57 CPU cores
arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC
arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins
arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM
arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM
arm64: dts: r8a7795: Add Cortex-A53 PMU node
arm64: dts: r8a7795: Add Cortex-A53 CPU cores
arm64: dts: r8a7796: Enable HSCIF DMA
arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1)
arm64: dts: r8a7796: Enable SCIF DMA
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
#include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Per e-mail from Sergei Shtylyov, the DT spec dictates it should be
"okay" (although "ok" is also recognized). Thus, changing all "ok" to
"okay" in NS2 device tree files
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk and pcie_bus_clk device nodes are already enabled in
r8a7795.dtsi, so there is no need to update their statuses again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7795.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
These UniPhier DT files are fine as long as they are compiled in the
Linux build system. It is true that Linux is the biggest user of
DT, but DT is project neutral from its concept. DT files are often
re-used for other projects. Especially for the UniPhier platform,
these DT files are re-used for U-Boot as well.
If I feed these DT files to the FDTGREP tool in U-Boot, it complains
about the node order.
FDTGREP spl/u-boot-spl.dtb
Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
/aliases node must come before all other nodes
Given that DT is not very sensitive to the order of nodes, this is a
problem of FDTGREP. I filed a bug report a year ago, but it has not
been fixed yet.
Differentiating DT is painful. So, I am up-streaming the requirement
from the down-stream project.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable the performance monitor unit for the Cortex-A53 cores on the
R8A7796 SoC.
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of
6 cores (2 x Cortex-A57 + 4 x Cortex-A53).
Based on a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable the performance monitor unit for the Cortex-A57 cores on the
R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of
2 x Cortex-A57.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Rebased]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
A gpio expander is present on the i2c bus on the Armada 3720 DB board. This
patch add it to the device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
These property were missing when the nodes were added and their lack
generate warning messages when adding i2c device in the subnodes.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This RTC IP is found in the CP110 master and slave which are part of the
Armada 8K SoCs and of the subset family the Armada 7K.
There is one RTC in each CP but the RTC requires an external
oscillator. However on the Armada 80x0, the RTC clock in CP master is not
connected (by package) to the oscillator. So this one is disabled for the
Armada 8020 and the Armada 8040.
As the RTC clock in CP slave is connected to the oscillator this one is
let enabled. and will be used on these SoCs (80x0).
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on audio data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The EthernetAVB should not depend on the bootloader to setup correct
drive-strength values. Values for drive-strength where found by
examining the registers after the bootloader has configured the
registers and successfully used the EthernetAVB.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A57 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 1561f20760 ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A57/A53 cache controllers are integrated controllers, and
thus the device nodes representing them should not have unit-addresses
or reg properties.
Fixes: 6f7bf82cc9 ("arm64: dts: r8a7795: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI
function call. Hence, upgrade PSCI version for R-Car M3-W to support
Suspend-to-RAM.
The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support
since necessary callback functions will be registered after a query
to ARM Trusted Firmware about SYSTEM_SUSPEND support.
Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and
CPUIdle should be able to work normally with this change.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Keep "arm,psci-0.2"]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI
function call. Hence, upgrade PSCI version for R-Car H3 to support
Suspend-to-RAM.
The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support
since necessary callback functions will be registered after a query
to ARM Trusted Firmware about SYSTEM_SUSPEND support.
Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and
CPUIdle should be able to work normally with this change.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Keep "arm,psci-0.2"]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable the performance monitor unit for the Cortex-A53 cores on the
R8A7795 SoC.
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Based on work by Takeshi Kihara and Dirk Behme.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enables the SCIF hooked up to the DEBUG1 connector.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
