Commit graph

4186 commits

Author SHA1 Message Date
Luca Porzio
d3df0465db mmc: remove bondage between REQ_META and reliable write
Anytime a write operation is performed with Reliable Write flag enabled,
the eMMC device is enforced to bypass the cache and do a write to the
underling NVM device by Jedec specification; this causes a performance
penalty since write operations can't be optimized by the device cache.

In our tests, we replayed a typical mobile daily trace pattern and found
~9% overall time reduction in trace replay by using this patch. Also the
write ops within 4KB~64KB chunk size range get a 40~60% performance
improvement by using the patch (as this range of write chunks are the ones
affected by REQ_META).

This patch has been discussed in the Mobile & Embedded Linux Storage Forum
and it's the results of feedbacks from many people. We also checked with
fsdevl and f2fs mailing list developers that this change in the usage of
REQ_META is not affecting FS behavior and we got positive feedbacks.
Reporting here the feedbacks:
http://comments.gmane.org/gmane.linux.file-systems/97219
http://thread.gmane.org/gmane.linux.file-systems.f2fs/3178/focus=3183

Signed-off-by: Bruce Ford <bford@micron.com>
Signed-off-by: Luca Porzio <lporzio@micron.com>
Fixes: ce39f9d17c ("mmc: support packed write command for eMMC4.5 devices")
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 14:04:52 +01:00
Geert Uytterhoeven
3d35877294 mmc: MMC_GOLDFISH should depend on HAS_DMA
If NO_DMA=y:

    ERROR: dma_unmap_sg [drivers/mmc/host/android-goldfish.ko] undefined!
    ERROR: dma_alloc_coherent [drivers/mmc/host/android-goldfish.ko] undefined!
    ERROR: dma_map_sg [drivers/mmc/host/android-goldfish.ko] undefined!
    ERROR: dma_free_coherent [drivers/mmc/host/android-goldfish.ko] undefined!

Add a dependency on HAS_DMA to fix this.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:16:45 +01:00
Geert Uytterhoeven
62d494ca27 mmc: mediatek: Preinitialize delay_phase in get_best_delay()
drivers/mmc/host/mtk-sd.c: In function ‘get_best_delay’:
drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.start’ is used uninitialized in this function
drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.maxlen’ is used uninitialized in this function

If delay is zero, these fields are indeed not initialized.
Let the compiler preinitialize the whole struct to fix this.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:16:44 +01:00
Adrian Hunter
d23029332c mmc: mmc: Improve reliability of mmc_select_hs400()
mmc_select_hs400() calls __mmc_switch() which checks the switch is
successful using CMD13 (SEND_STATUS).  The problem is that it does that
using the timing settings of the previous mode.  That is prone to error,
especially when switching from HS to HS400 because the timing parameters
for HS mode are tighter than the timing parameters for HS400 mode.

In the case when CMD13 polling is used (i.e. not MMC_CAP_WAIT_WHILE_BUSY)
with the switch command, it must be assumed that using different modes on
the card and host must work.

However in the case when CMD13 polling is not used
(i.e. MMC_CAP_WAIT_WHILE_BUSY) mmc_select_hs400() can be made more
reliable by setting the host to the correct timing before sending CMD13.

This patch does that.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: <stable@vger.kernel.org> # 4.2+
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:16:32 +01:00
Adrian Hunter
974007aaf2 mmc: mmc: Move mmc_switch_status()
Move the mmc_switch_status() function in preparation for calling it
in mmc_select_hs400().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: <stable@vger.kernel.org> # 4.2+
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:16:26 +01:00
Adrian Hunter
51b12f7764 mmc: mmc: Fix HS setting in mmc_select_hs400()
mmc_select_hs400() begins with the card and host in HS200 mode.
Therefore, any commands sent to the card should use HS200 timing.
It is incorrect to set the host to High Speed (HS) timing before
sending the switch command.  Doing so is unreliable because
the timing parameters for HS mode are tighter than the timing
parameters for HS200 mode.  Thus the HS timings should be set
only after the card has switched mode.

However, it is not unreasonable first to reduce the frequency to
the HS mode frequency, which should make the switch command and
subsequent CMD13 commands more reliable.

This patch does that.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: <stable@vger.kernel.org> # 4.2+
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:16:20 +01:00
Adrian Hunter
1815e61b1a mmc: mmc: Improve reliability of mmc_select_hs200()
Currently mmc_select_hs200() uses __mmc_switch() which checks the
success of the switch to HS200 mode using CMD13 (SEND_STATUS).
The problem is that it does that using the timing settings of legacy
mode.  That is prone to error, not least because the timing parameters
for legacy mode are tighter than the timing parameters for HS200 mode.

In the case when CMD13 polling is used (i.e. not MMC_CAP_WAIT_WHILE_BUSY)
with the switch command, it must be assumed that using different modes on
the card and host must work.

However in the case when CMD13 polling is not used
(i.e. MMC_CAP_WAIT_WHILE_BUSY) mmc_select_hs200() can be made more
reliable by setting the host to the correct timing before sending CMD13.

This patch does that.

A complication is that the caller, mmc_select_timing(), will ignore a
switch error (indicated by -EBADMSG), assume the old mode is valid
and continue, so the old timing must be restored in that case.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: <stable@vger.kernel.org> # 4.2+
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:12:08 +01:00
Robert Jarzmik
26d49fe719 mmc: pxamci: fix read-only gpio detection polarity
The commit converting pxamci to slot-gpio API inverted the logic of the
read-only gpio. Fix it by inverting the logic again.

Fixes: fd546ee6a7 ("mmc: pxamci: fix card detect with slot-gpio API")
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-11-09 13:04:03 +01:00
Linus Torvalds
75f5db39ff spi: Updates for v4.4
Quite a lot of activity in SPI this cycle, almost all of it in drivers
 with a few minor improvements and tweaks in the core.
 
  - Updates to pxa2xx to support Intel Broxton and multiple chip selects.
  - Support for big endian in the bcm63xx driver.
  - Multiple slave support for the mt8173
  - New driver for the auxiliary SPI controller in bcm2835 SoCs.
  - Support for Layerscale SoCs in the Freescale DSPI driver.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJWOehzAAoJECTWi3JdVIfQTPYH+wYMDG8gAIw2s0AJ4DvVe4qZ
 sOAm1UgUJZxssrEA6BNqbfM0dfRo+oQJKmRd0Dc5n7LEMsYHdI/5yKHk8PCS6ZzD
 iQyQCzbd0thDAqwuPaMP62cyPDHwyJX22VGTsgVnj6AZqAQ+9+g4SPKhFnm1Mlm4
 hmDi6fdSrsqo8k8gkpVN8RFOfVsjAV1dLtAauQRWDHrqMxXURSrKG76eqAqUa5bn
 BLPXBoj5PA0DMLPO2j+ADZwWN723LrI2mSSlc+ThjEX/OIt2OhAoiOTV5RPqaafy
 TIsCkh68q/gYAsL5HtvvmgZByl41FLYiO0Z+rXmWUyMMbnvhZTLws9S2BNpBLuk=
 =DgXG
 -----END PGP SIGNATURE-----

Merge tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "Quite a lot of activity in SPI this cycle, almost all of it in drivers
  with a few minor improvements and tweaks in the core.

   - Updates to pxa2xx to support Intel Broxton and multiple chip selects.
   - Support for big endian in the bcm63xx driver.
   - Multiple slave support for the mt8173
   - New driver for the auxiliary SPI controller in bcm2835 SoCs.
   - Support for Layerscale SoCs in the Freescale DSPI driver"

* tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits)
  spi: pxa2xx: Rework self-initiated platform data creation for non-ACPI
  spi: pxa2xx: Add support for Intel Broxton
  spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals
  spi: pxa2xx: Add output control for multiple Intel LPSS chip selects
  spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific
  spi: Add DSPI support for layerscape family
  spi: ti-qspi: improve ->remove() callback
  spi/spi-xilinx: Fix race condition on last word read
  spi: Drop owner assignment from spi_drivers
  spi: Add THIS_MODULE to spi_driver in SPI core
  spi: Setup the master controller driver before setting the chipselect
  spi: dw: replace magic constant by DW_SPI_DR
  spi: mediatek: mt8173 spi multiple devices support
  spi: mediatek: handle controller_data in mtk_spi_setup
  spi: mediatek: remove mtk_spi_config
  spi: mediatek: Update document devicetree bindings to support multiple devices
  spi: fix kernel-doc warnings about missing return desc in spi.c
  spi: fix kernel-doc warnings about missing return desc in spi.h
  spi: pxa2xx: Align a few defines
  spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select
  ...
2015-11-05 13:15:12 -08:00
Mark Brown
4c84518523 Merge remote-tracking branches 'spi/topic/omap-100k', 'spi/topic/omap-uwire', 'spi/topic/owner', 'spi/topic/pxa' and 'spi/topic/pxa2xx' into spi-next 2015-11-04 11:02:12 +00:00
Jaehoon Chung
7cc8d58022 mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode
When card is running with DDR mode, dwmmc needs to set DDR_REG bit at
UHS_REG register.
Before this patch, dwmmc controller doesn't consider this.
If this patch is not applied, CRC or other error shoulds be occurred.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-29 11:00:43 +01:00
Jaehoon Chung
98daafd8a0 mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register
According to DesignWare DoC file, CardThreshold bit should be
bit[27:16].
So it's correct to use (0xFFF << 16), not (0x1FFF << 16).

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-29 11:00:37 +01:00
Dan Carpenter
4539d36ef2 mmc: dw_mmc: NULL dereference in error message
The "host->dms->ch" pointer is NULL here so we can't use it to print the
error message.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-29 11:00:03 +01:00
Andrew F. Davis
3821a065f5 spi: Drop owner assignment from spi_drivers
An spi_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-28 10:30:17 +09:00
Javier Martinez Canillas
1c6e58d836 mmc: pwrseq: Use highest priority for eMMC restart handler
The pwrseq_emmc driver does a eMMC card reset before a system reboot to
allow broken or limited ROM boot-loaders (that don't have an eMMC reset
logic) to be able to read the second stage from the eMMC.

But this has to be called before a system reboot handler and while most
of them use the priority 128, there are other restart handlers (such as
the syscon-reboot one) that use a higher priority. So, use the highest
priority to make sure that the eMMC hw is reset before a system reboot.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 11:11:06 +01:00
Chaotian Jing
6397b7f5f4 mmc: mediatek: add HS400 support
add HS400 mode and tune support

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:40:38 +01:00
Chaotian Jing
9979dbe515 mmc: mmc: extend the mmc_send_tuning()
The mmc_execute_tuning() has already prepared the opcode,
there is no need to prepare it again at mmc_send_tuning(),
and, there is a BUG of mmc_send_tuning() to determine the opcode
by bus width, assume eMMC was running at HS200, 4bit mode,
then the mmc_send_tuning() will overwrite the opcode from CMD21
to CMD19, then got error.

in addition, extend an argument of "cmd_error" to allow getting
if there was cmd error when tune response.

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
[Ulf: Rebased patch]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:38:41 +01:00
Chaotian Jing
c9b5061e77 mmc: mediatek: add implement of ops->hw_reset()
add implement of ops->hw_reset() for eMMC

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:21:16 +01:00
Chaotian Jing
62b0d27af8 mmc: mediatek: fix got GPD checksum error interrupt when data transfer
Even if we only use one gpd, we need alloc 2 gpd and make
the gpd->next pointer to the second gpd, or may get gpd checksum
error, this was checked by hardware

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:21:16 +01:00
Chaotian Jing
6e622947e1 mmc: mediatek: change the argument "ddr" to "timing"
use the ios->timing directly is better
It can reflect current timing and do settings by timing

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:21:16 +01:00
Chaotian Jing
726a9aac31 mmc: mediatek: make cmd_ints_mask to const
cmd_ints_mask and data_ints_mask are constant value,
so make it to const

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:21:15 +01:00
Chaotian Jing
794f15782d mmc: core: Add DT bindings for eMMC hardware reset support
Sometime only need set MMC_CAP_HW_RESET for one of MMC hosts,
So set it in device tree is better.

Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-27 10:21:15 +01:00
Lokesh Vutla
a7cedab6cc mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2
Enable omap_hsmmc for Keystone 2 architecture which reuses the HSMMC
IP found on OMAP platforms.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:20 +01:00
Adrian Hunter
e839b13476 mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllers
Add ACPI HIDs for Intel host controllers including one
supporting HS400.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:20 +01:00
Adrian Hunter
4fd4c0655b mmc: sdhci-pci: Add more PCI IDs for Intel controllers
Add PCI IDs for Intel host controllers

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:19 +01:00
Shawn Lin
70692752af mmc: dw_mmc: use macro for HCON register operations
This patch add some macros for HCON register operations
to make code more readable.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:16 +01:00
Shawn Lin
3fc7eaef44 mmc: dw_mmc: Add external dma interface support
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK31xx
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:16 +01:00
yangbo lu
9e4703df3a mmc: sdhci-of-esdhc: avoid writing power control register
The eSDHC doesn't have a standard power control register, so when
writing this register in stack we should do nothing to avoid
incorrect operation.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:15 +01:00
Sergei Shtylyov
2860d060ac mmc: skip reclaiming host on mmc_add_card() error
There's little sense in releasing the host on mmc_add_card() error
immediately after reclaiming  it, so reclaim the host  only in case
of success.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:14 +01:00
Luis de Bethencourt
7f8a9a7e98 mmc: android-goldfish: Allow compiling the driver with COMPILE_TEST
The driver depends on GOLDFISH but there isn't a build dependency
so it's a good idea to allow the driver to always be built when the
COMPILE_TEST option is enabled.

That way, the driver can be built with a config generated by make
allyesconfig and check if a patch would break the build.

Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:13 +01:00
Alexandru M Stan
cbb79e43c8 mmc: dw_mmc-rockchip: MMC tuning with the clock phase framework
This algorithm will try 1 degree increments, since there's no way to tell
what resolution the underlying phase code uses. As an added bonus, doing
many tunings yields better results since some tests are run more than once
(ex: if the underlying driver uses 45 degree increments, the tuning code
will try the same angle more than once).

It will then construct a list of good phase ranges (even ranges that cross
360/0), will pick the biggest range then it will set the sample_clk to the
middle of that range.

We do not touch ciu_drive (and by extension define default-drive-phase).
Drive phase is mostly used to define minimum hold times, while one could
write some code to determine what phase meets the minimum hold time (ex 10
degrees) this will not work with the current clock phase framework (which
floors angles, so we'll get 0 deg, and there's no way to know what
resolution the floors happen at). We assume that the default drive angles
set by the hardware are good enough.

If a device has device specific code (like exynos) then that will still
take precedence, otherwise this new code will execute. If the device wants
to tune, but has no sample_clk defined we'll return EIO with an error
message.

Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:12 +01:00
Douglas Anderson
e0848f5d29 mmc: dw_mmc: Use mmc_regulator_set_vqmmc in start_signal_voltage_switch
We've introduced a new helper in the MMC core:
mmc_regulator_set_vqmmc().  Let's use this in dw_mmc.  Using this new
helper has some advantages:

1. We get the mmc_regulator_set_vqmmc() behavior of trying to match
   VQMMC and VMMC when the signal voltage is 3.3V.  This ensures max
   compatibility.

2. We get rid of a few more warnings when probing unsupported
   voltages.

3. We get rid of some non-dw_mmc specific code in dw_mmc.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:11 +01:00
Douglas Anderson
2086f801cb mmc: core: Add mmc_regulator_set_vqmmc()
This adds logic to the MMC core to set VQMMC.  This is expected to be
called by MMC drivers like dw_mmc as part of (or instead of) their
start_signal_voltage_switch() callback.

A few notes:

* When setting the signal voltage to 3.3V we do our best to make VQMMC
  and VMMC match.  It's been reported that this makes some old cards
  happy since they were tested back in the day before UHS when VQMMC
  and VMMC were provided by the same regulator.  A nice side effect of
  this is that we don't end up on the hairy edge of VQMMC (2.7V),
  which some EEs claim is a little too close to the minimum for
  comfort.
  This is done in two steps. At first we try to find a VQMMC within
  a 0.3V tolerance of VMMC and if this is not supported by the
  supplying regulator we try to find a suitable voltage within the
  whole 2.7V-3.6V area of the spec.

* The two step approach is currently necessary, as the used
  regulator_set_voltage_triplet(min, target, max) uses a simple
  implementation that just tries two basic steps:
	regulator_set_voltage(target, max);
	regulator_set_voltage(min, target);
  So with only one step with 2.7-3.6V borders, if a suitable voltage
  is a bit below VMMC, we would directly get the lowest 2.7V
  which some boards (like Rockchips) don't like at all.

* When setting the signal voltage to 1.8V or 1.2V we aim for that
  specific voltage instead of picking the lowest one in the range.

* We very purposely don't print errors in mmc_regulator_set_vqmmc().
  There are cases where the MMC core will try several different
  voltages and we don't want to pollute the logs.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:10 +01:00
Heiko Stuebner
310c805e7f mmc: core: move ocr-bit to voltage translation into separate function
We will shortly need the calculation of an ocr-bit to the actual
voltage in a second place too, so move it from mmc_regulator_set_ocr
to a common function mmc_ocrbitnum_to_vdd to make that possible.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:10 +01:00
Ulf Hansson
9eadcc0581 mmc: core: Remove MMC_CLKGATE
MMC_CLKGATE was once invented to save power by gating the bus clock at
request inactivity. At that time it served its purpose. The modern way to
deal with power saving for these scenarios, is by using runtime PM.

Nowadays, several host drivers have deployed runtime PM, but for those
that haven't and which still cares power saving at request inactivity,
it's certainly time to deploy runtime PM as it has been around for several
years now.

To simplify code to mmc core and thus decrease maintenance efforts, this
patch removes all code related to MMC_CLKGATE.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-26 16:00:09 +01:00
yangbo lu
a22950c888 mmc: sdhci-of-esdhc: add quirk SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for ls1021a
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:09 +01:00
yangbo lu
2ca635242e mmc: kconfig: reconfigure MMC_SDHCI_OF_ESDHC option
Freescale eSDHC driver now supports both little-endian and
big-endian mode eSDHC IPs for ARM and PPC. So, MMC_SDHCI_OF_ESDHC
option needs to be reconfigured.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:08 +01:00
yangbo lu
f4932cfd22 mmc: sdhci-of-esdhc: support both BE and LE host controller
To support little endian eSDHC controller, we redefine both BE and
LE IO accessors. In the new accessors, use ioread*/iowrite* instead
of in_be32/out_be32 and will select accessors according to endian
mode in probe function.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:08 +01:00
Adrian Hunter
06bf9c5654 mmc: sdhci-pci: Add another PCI ID for an Intel eMMC host controller
Add another PCI ID for an Intel eMMC host controller.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:07 +01:00
kbuild test robot
7582041ff3 mmc: sdhci-pci: fix simple_return.cocci warnings
drivers/mmc/host/sdhci-pci-core.c:447:1-4: WARNING: end returns can be simpified

 Simplify a trivial if-return sequence.  Possibly combine with a
 preceding function call.

Generated by: scripts/coccinelle/misc/simple_return.cocci

CC: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:06 +01:00
Ben Hutchings
f0cbd7806d mmc: sdhci-pci: Make sdhci_pci_o2_fujin2_pci_init() static
It has no external callers.

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:05 +01:00
Ben Hutchings
659c9bc114 mmc: sdhci-pci: Build o2micro support in the same module
sdhci-pci-o2micro.c contains no initialisation and its functions are only
called from shdci-pci.c, so there is no reason for it to be a separate
module, let alone or for it to always be built-in.

- Rename sdhci-pci.c to sdhci-pci-core.c so that the sdhci-pci module
  can be built from multiple source files
- Add sdhci-pci-o2micro.c to it
- Remove redundant exports

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:05 +01:00
Weijun Yang
0de9125fa8 mmc: sirf: fix the capbility to support DDR50
According to hardware spec, validate DDR50 mode
for SDXC.

Signed-off-by: Weijun Yang <york.yang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:04 +01:00
Weijun Yang
9faac7b95e mmc: sdhci: enable tuning for DDR50
CMD19 tuning is also available for DDR50 mode.

Signed-off-by: Weijun Yang <york.yang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:04 +01:00
Weijun Yang
4324f6de6d mmc: core: enable CMD19 tuning for DDR50 mode
As SD Specifications Part1 Physical Layer Specification Version
3.01 says, CMD19 tuning is available for unlocked cards in transfer
state of 1.8V signaling mode. The small difference between v3.00
and 3.01 spec means that CMD19 tuning is also available for DDR50
mode.

Signed-off-by: Weijun Yang <york.yang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:03 +01:00
Grant Grundler
b093410c9a mmc: block: copy resp[] data on err for MMC_IOC_MULTI_CMD
MMC_IOC_CMD and MMC_IOC_MULTI_CMD ioctl() code currently bails on
any eMMC errors. However, in case there is any resp[] data, we
should attempt to copy resp[] back to user space. The user app
can then determine which command(s) failed in the MMC_IOC_MULTI_CMD
case AND/OR report better diagnostics in both cases.

Gwendal Grignou provided the idea and it was previously implemented
and tested on v3.18 ChromeOS kernel:
    https://chromium-review.googlesource.com/#/c/299956

Signed-off-by: Grant Grundler <grundler@chromium.org>
Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Tested-by: David Riley <davidriley@chromium.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:03 +01:00
Shawn Lin
85f45058ee mmc: debugfs: implement ios show for SDR12 and SDR25
This patch add MMC_TIMING_UHS_SDR12 and MMC_TIMING_UHS_SDR25
for mmc_ios_show to show the ios->timing if mmc card runs under
these two modes.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:02 +01:00
Hans de Goede
c1590dd86d mmc: sunxi: Add card busy detection
Some sdio wifi modules have not been working reliable with the sunxi-mmc
host code. This turns out to be caused by starting new io-rw commands while
the card signals that it is still busy processing a previous command.

This commit adds card-busy detection to the sunxi-mmc driver which together
with recent core changes to check card-busy before starting io-rw commands
fixes the wifi reliability issues on the Cubietruck and other sunxi boards
using sdio wifi.

Reported-by: Eugene K <sigintmailru@gmail.com>
Suggested-by: Eugene K <sigintmailru@gmail.com>
Cc: Eugene K <sigintmailru@gmail.com>
Cc: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:02 +01:00
Hans de Goede
5d3f6ef04d mmc: Wait for card_busy before starting sdio requests
Some sdio wifi chips will not work properly if we try to start new
sdio-rw requests while the device is signalling that it is busy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:01 +01:00
Hans de Goede
de98c55682 mmc: Add mmc_is_io_op helper function
Add a helper function to check if an opcode is a sd-io-rw-* opcode.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:01 +01:00