Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The members of struct cros_ec_device were improperly commented, and
intermixed the private and public sections. This is just cleanup to make it
more obvious what goes with what.
[dianders: left lock in the structure but gave it the name that will
eventually be used.]
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Set the device as wakeup capable and register the wakeup source.
Note: Though it makes more sense to have the SPI framework do this,
(either via device tree or by board_info)
this change is as per an existing mail chain:
https://lkml.org/lkml/2009/8/27/291
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
cros_ec_spi makes the assumption that a 0-length message will put the
spi chip select back to normal (non cs_toggle mode). This used to be
the case back on kernel-3.8 on the spi-s3c64xx driver but doesn't
appear to be true anymore. It seems like it was a pretty questionable
assumption to begin with, so let's fix the code to be more robust. We
know that a message with a single 0-length segment _will_ put things
back in order. Change cros_ec_spi to handle this.
This wasn't a problem on the main user of cros_ec_spi upstream (tegra)
because it specified 'google,cros-ec-spi-msg-delay'.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
We're adding i2c tunneling to the list of things that goes over
cros_ec. i2c tunneling can be slooooooow, so increase our deadline to
100ms to account for that.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The cros_ec_spi transfer had two problems with its timeout code:
1. It looked at the timeout even in the case that it found valid data.
2. If the cros_ec_spi code got switched out for a while, it's possible
it could get a timeout after a single loop. Let's be paranoid and
make sure we do one last transfer after the timeout expires.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The main transfer function for cros_ec_spi can be called by more than
one client at a time. Make sure that those clients don't stomp on
each other by locking the bus for the duration of the transfer
function.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
To avoid spamming the EC we calculate the time between the previous
transfer and the current transfer and force a delay if the time delta
is too small.
However, a small miscalculation causes the delay period to be
far too short. Most noticably this impacts commands with a long
turnaround time such as EC firmware reads and writes.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The EC has specific timing it requires. Add support for an optional delay
after raising CS to fix timing issues. This is configurable based on
a DT property "google,cros-ec-spi-msg-delay".
If this property isn't set, then no delay will be added. However, if set
it will cause a delay equal to the value passed to it to be inserted at
the end of a transaction.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
memset() was being called with the second parameter set to '\0', which
is equivalent but longer than the more canonical 0. Update the code to
use the latter variant consistently across the driver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
According to the header comment in the source file the driver is
licensed under GPL v2, so update MODULE_LICENSE() to match that.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Rename cros_ec_{probe,remove}_spi() to cros_ec_spi_{probe,remove}() for
consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The dev_cont() symbol doesn't exist, so replace it with pr_cont(). While
at it, also append a newline to the debug output to make it look nicer.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
50 us is not a long enough delay between EC transactions. At least 70 us
are needed for the 16 MHz STM32L part. Increase the delay to 200 us for
an extra safety margin.
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Before commit 5c29e47e6a ("mfd: cros_ec_spi:
Warnings fix"), 64-bit compiles gave the following warnings:
drivers/mfd/cros_ec_spi.c: In function 'cros_ec_spi_receive_response':
drivers/mfd/cros_ec_spi.c:123:5: warning: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Wformat]
drivers/mfd/cros_ec_spi.c:157:3: warning: format '%d' expects argument of type 'int', but argument 6 has type 'long int' [-Wformat]
drivers/mfd/cros_ec_spi.c:181:2: warning: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Wformat]
After that commit, 32-bit compiles give:
drivers/mfd/cros_ec_spi.c: In function ‘cros_ec_spi_receive_response’:
drivers/mfd/cros_ec_spi.c:123: warning: format ‘%ld’ expects type ‘long int’, but argument 4 has type ‘int’
drivers/mfd/cros_ec_spi.c:157: warning: format ‘%ld’ expects type ‘long int’, but argument 6 has type ‘int’
drivers/mfd/cros_ec_spi.c:181: warning: format ‘%ld’ expects type ‘long int’, but argument 4 has type ‘int’
Use %z to format pointer differences to kill the warnings on both 32-bit
and 64-bit.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
To silent those:
CC [M] drivers/mfd/cros_ec_spi.o
drivers/mfd/cros_ec_spi.c: In function ‘cros_ec_spi_receive_response’:
drivers/mfd/cros_ec_spi.c:123:5: warning: format ‘%d’ expects argument of type
‘int’, but argument 4 has type ‘long int’ [-Wformat]
drivers/mfd/cros_ec_spi.c:157:3: warning: format ‘%d’ expects argument of type
‘int’, but argument 6 has type ‘long int’ [-Wformat]
drivers/mfd/cros_ec_spi.c:181:2: warning: format ‘%d’ expects argument of type
‘int’, but argument 4 has type ‘long int’ [-Wformat]
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This uses a SPI bus to talk to the ChromeOS EC. The protocol
is defined by the EC and is fairly simple, with a length byte,
checksum, command byte and version byte (to permit easy creation
of new commands).
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
