Commit graph

6 commits

Author SHA1 Message Date
Bryan Wu
8fef5dffde ARM: DT: tegra: Unify the description of Tegra20 boards
Use engineering name 'Tegra20' instead of 'Tegra2'

Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:24:06 -07:00
Stephen Warren
2658ef15b2 ARM: tegra: whistler: enable HDMI port
Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD,
and a VGA output. tegradrm doesn't support either of those output types
yet.

Based on work by Thierry Reding for TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 10:56:38 -07:00
Stephen Warren
b9c665d75b ARM: tegra: update *.dts for regulator-compatible deprecation
Commit 13511de "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
2012-11-05 11:36:04 -07:00
Stephen Warren
b37ed4a3e5 ARM: dt: tegra: whistler: configure power off
Add DT property to tell the MAX8907 that it should provide the
pm_power_off() implementation. This allows "shutdown" to work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-19 10:19:38 -06:00
Stephen Warren
e7765b3746 ARM: dt: tegra: whistler: add regulators
Whistler uses a Maxim 8907 regulator. Instantiate this.

The voltage settings were derived from the schematic. The only exception
is the BBAT voltage; the schematic says 1.2v, but the HW can't go that
low, so use the HW default of 2.4v instead.

Almost all regulators list all driven supply signal names in their
regulator-names property. The exception is nvvdd_sv3, which is in turn
named 12 more different names on the schematic, so these were omitted
for brevity.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-06 11:48:39 -06:00
Stephen Warren
c80efbae6a ARM: dt: tegra: add Whistler device tree file
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:

E1120 motherboard
E1108 CPU board
E1116 PMU board

The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.

Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-07-06 12:27:35 -06:00