Add these PCI class codes to pci_ids.h:
PCI_CLASS_BRIDGE_PCI_NORMAL
PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE
Use these defines in all kernel code for describing PCI class codes for
normal and subtractive PCI bridges.
[bhelgaas: similar change in pci-mvebu.c]
Link: https://lore.kernel.org/r/20220214114109.26809-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Using a mask to represent bus DMA constraints has a set of limitations.
The biggest one being it can only hold a power of two (minus one). The
DMA mapping code is already aware of this and treats dev->bus_dma_mask
as a limit. This quirk is already used by some architectures although
still rare.
With the introduction of the Raspberry Pi 4 we've found a new contender
for the use of bus DMA limits, as its PCIe bus can only address the
lower 3GB of memory (of a total of 4GB). This is impossible to represent
with a mask. To make things worse the device-tree code rounds non power
of two bus DMA limits to the next power of two, which is unacceptable in
this case.
In the light of this, rename dev->bus_dma_mask to dev->bus_dma_limit all
over the tree and treat it as such. Note that dev->bus_dma_limit should
contain the higher accessible DMA address.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The Broadcom SiByte BCM1250, BCM1125H and BCM1125 SOCs have an onchip
32-bit PCI host bridge, and the two former SOCs also have an onchip HT
host bridge. The HT host bridge, where present, appears in the PCI
configuration space as if it was a device on the 32-bit PCI bus behind
the PCI host bridge, however at the hardware level its signals are
routed separately, so these two devices are actually peer host bridges.
As documented[1] and observed in reality the 32-bit PCI host bridge does
not support 64-bit addressing as it does not support the Dual Address
Cycle (DAC) PCI command, and naturally, being 32-bit only, it has no
means to carry the high 32 address bits otherwise. However the DRAM
controller also included in the SOC supports memory amounts of up to
16GiB, and due to how the address decoder has been wired in the SOC any
memory beyond 1GiB is actually mapped starting from 4GiB physical up,
that is beyond the 32-bit addressable limit. Consequently if the
maximum amount of memory has been installed, then it will span up to
19GiB.
Contrariwise, the HT host bridge does support full 40-bit addressing
defined by the HyperTransport (formerly LDT) specification the bridge
adheres to, depending on the peripherals revision of the SOC[2] either
revision 0.17[3] or revision 1.03[4]. This allows addressing any and
all memory installed, and well beyond.
Set the bus mask then to limit DMA addressing to 32 bits for all the
devices down the 32-bit PCI host bridge, excluding however any devices
that are down the HT host bridge.
References:
[1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R,
Broadcom Corporation, 21 Oct 2002, Section 8: "PCI Bus and
HyperTransport Fabric", "Introduction", p. 190
[2] same, Table 140: "HyperTransport Configuration Header (Type 1)", p.
245
[3] "Lightning Data Transport IO Specification", Revision 0.17, Advanced
Micro Devices, 21 Jan 2000, Section 3.2.1.2 "Command Packet", p. 8
[4] "HyperTransport I/O Link Specification", Revision 1.03,
HyperTransport Technology Consortium, 10 Oct 2001, Section 3.2.1.2
"Request Packet", pp. 27-28
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Patchwork: https://patchwork.linux-mips.org/patch/21106/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6320/
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Fixups are executed once the pci-device is found which is during boot
process so __init seems fine as long as the platform does not support
hotplug.
However it is possible to remove the PCI bus at run time and have it
rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call
the fixups again.
[ralf@linux-mips.org: Made piixirqmap[] in malta_piix_func0_fixup()
__initdata.]
Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
They tend to get not updated when files are moved around or copied and
lack any obvious use. While at it zap some only too obvious comments and
as per Shinya's suggestion, add a copyright header to extable.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
It was obesrved that at least one older PCI card predating the
requirement for the TRDY signal to respond within 16 clock ticks actually
does not meet this rule nor even the power-on defaults of the PCI bridges
found in development systems built around the Broadcom SiByte SOCs. Here
is a patch that bumps up the timeout to the highest finite value supported
by these chips, which is 255 clock ticks. The bridges affected are the
SiByte SOC itself and the SP1011.
This change does not effectively affect systems only having PCI option
cards installed that meet the TRDY requirement of the current PCI spec.
The rule was introduced with PCI 2.1, so any older card may make the
system affected. If this is the case, performance of the system will
suffer in return for the card working at all. If this is a concern, then
the solution is not to use such cards.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
