There is a potential race when two threads do the writes to the same register
in parallel.
Prevent out of order in such case by protecting I/O access by spin lock.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Intel Merrifield platform has a special GPIO controller to
drive pads when they are muxed in corresponding mode.
Intel Merrifield GPIO IP is slightly different here and there
in comparison to the older Intel MID platforms. These differences
include in particular the shaked register offsets, specific
support of level triggered interrupts and wake capable sources,
as well as a pinctrl which is a separate IP.
Instead of uglifying existing driver I decide to provide a new
one slightly based on gpio-intel-mid.c. So, anyone can easily
compare what changes are happened to be here.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Brian J Wood <brian.j.wood@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
