Not really sure how to confirm this 100%, but, the numbers match on all the
traces I have for NVCx (2 LTS), NVD9 (1LTS) and NVEx (4LTS).
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Triggers PIBUS interrupts due to register not existing anymore, and as
a result HUB_SET_CHAN times out.
After this commit, our fuc loads and can accelerate at least fbcon, X,
glxgears and OA on NVE4. NVE7 not tested as of yet.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Currently identical except the available chipset register lists. This will
*not* currently work and is disabled by default because of this.
May get merged again later, remains to be seen what further changes will be
required.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Future code will use the object class rather than chipset checks in order to
identify available channel features.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This value will match something that's easily available from the engine IRQ
handlers, and used to lookup the relevant context.
Since the changes in how this is done on each generation match when the
major PFIFO changes happened, fifo is responsible for calculating the
correct value to avoid duplicating the same code among many engine modules.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Kepler PFIFO lost the ability to address multiple engines from a single
channel, so we need a separate one for the copy engine.
v2: Marcin Slusarz <marcin.slusarz@gmail.com>
- regression fix: restore hw accelerated buffer copies
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
v2: Ben Skeggs <bskeggs@redhat.com>
- fill in nouveau_pm.dev to prevent oops
- fix ppc issues (build + OF shadow)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This is a HUGE commit, but it's not nearly as bad as it looks - any problems
can be isolated to a particular chipset and engine combination. It was
simply too difficult to port each one at a time, the compat layers are
*already* ridiculous.
Most of the changes here are simply to the glue, the process for each of the
engine modules was to start with a standard skeleton and copy+paste the old
code into the appropriate places, fixing up variable names etc as needed.
v2: Marcin Slusarz <marcin.slusarz@gmail.com>
- fix find/replace bug in license header
v3: Ben Skeggs <bskeggs@redhat.com>
- bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and
left no space for kernel's requirements during GEM pushbuf submission.
- fix duplicate assignments noticed by clang
v4: Marcin Slusarz <marcin.slusarz@gmail.com>
- add sparse annotations to nv04_fifo_pause/nv04_fifo_start
- use ioread32_native/iowrite32_native for fifo control registers
v5: Ben Skeggs <bskeggs@redhat.com>
- rebase on v3.6-rc4, modified to keep copy engine fix intact
- nv10/fence: unmap fence bo before destroying
- fixed fermi regression when using nvidia gr fuc
- fixed typo in supported dma_mask checking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
v2: Ben Skeggs <bskeggs@redhat.com>
- de-inline nv_icmd, triggers some gcc issue causing ctxnv[ce]0.c to
take a *very* *very* long time to build on some configs.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This is all very much a policy thing, and hence will not belong in SW
after the rework.
engsw now only handles receiving the event to say "can flip now" and makes
a callback to perform the actual work.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
There's a *lot* of code in here, and it's all going to use the PGRAPH priv
pointer rather than drm_device after the engine rework. This is handling
all the rename-only parts of the change.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Still the same code, but not an "engine" anymore. The fence code is more of
a policy decision rather than exposing mechanisms, so it's not appropriate
to port it to the new engine subsystem.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
