add thermal zone and dynamic CPU power coefficients for rk3328
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
add tsadc needed main information for rk3328 SoC.
50000Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
BPi M64 has an AP6212 Wi-Fi/Bluetooth combo module, and the Wi-Fi SDIO
card is connected to the mmc1 controller.
The pwrseq of the mmc1 (used to reset the card) used to missing, and the
out-of-band interrupt line of the card is not specified.
Fix these issues for proper Wi-Fi support of BPi M64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Banana Pi M64 connects the USB host-only controller on A64 SoC to a USB
hub, which provided the two USB Type-A ports on the board.
Enable the USB host controller.
The OTG function of the Micro-USB port needs the drivevbus function of
the AXP803 driver implemented, so it's not enabled now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The EMAC Ethernet controller was enabled, but an accompanying alias
was not added. This results in unstable numbering if other Ethernet
devices, such as a USB dongle, are present. Also, the bootloader uses
the alias to assign a generated stable MAC address to the device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes: 96219b0048 ("arm64: allwinner: a64: add device tree for SoPine
with baseboard")
[wens@csie.org: Rewrite commit log as fixing a previous patch with Fixes]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The EMAC Ethernet controller was enabled, but an accompanying alias
was not added. This results in unstable numbering if other Ethernet
devices, such as a USB dongle, are present. Also, the bootloader uses
the alias to assign a generated stable MAC address to the device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes: 9702394374 ("arm64: allwinner: pine64: Enable dwmac-sun8i")
[wens@csie.org: Rewrite commit log as fixing a previous patch with Fixes]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The EMAC Ethernet controller was enabled, but an accompanying alias
was not added. This results in unstable numbering if other Ethernet
devices, such as a USB dongle, are present. Also, the bootloader uses
the alias to assign a generated stable MAC address to the device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes: e729549990 ("arm64: allwinner: bananapi-m64: Enable dwmac-sun8i")
[wens@csie.org: Rewrite commit log as fixing a previous patch with Fixes]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
On UniPhier platform, some DTSI files are shared between arm and arm64.
Recently, inclusion of DT material of different architectures has been
supported by the build system level. Use #include <arm/...>, which
will work without relying on the exact same hierarchy as the kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch switches to the stable UART bindings but also add the correct
gate clock to the non-AO UART nodes for GXBB and GXL SoCs.
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the smd-edge node for the adsp, to allow SMD communication with the
ADSP.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the SMP2P nodes for the modem.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Adding required device node for couple of DWC3 controllers
present on msm8996 chipset to enable High speed and Super
speed USB support.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add required device node for QMP phy based 3-lane PCIe phy
present on msm8996 chipset to enable support for the same.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Adding required device node for USB3 QMP phy present on
msm8996 chipset to enable support for the same. This phy
provides super speed usb functionality for dwc3 controller
on msm8996.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Adding device node for QUSB2 phy and the required infrastructure
to enable support for the same. This phy is used by dwc3 controller
present on msm8996.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The adv7533 on this board needs a cec clock. Hook it up in the dtsi
to enable CEC for the HDMI transmitters.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Commit ed75d6a969 ("arm64: dts: qcom: Collapse usb support into
one node") breaks host mode support on apq8016-sbc boards. This
is because the mux driver (tc7usb40mu) hasn't been merged.
Without that driver, we can't toggle the GPIO going to the mux to
route out the D+/D- lines to the USB hub that's on the board.
One solution would be to totally revert this change, but that
opens us up to other problems when two USB drivers are operating
the same hardware block at the same time. Let's modify the DT so
that the USB controller is always in host mode and connected to
the hub so that things like USB keyboards and mouses work. This
is the mode that most people prefer anyway with these devices. We
also delete the usb-switch node because the binding was never
accepted upstream.
In the future, we can add muxing support and then update the DT
to support both modes at runtime. Patches to support this are
already on the mailing list.
Fixes: ed75d6a969 ("arm64: dts: qcom: Collapse usb support into one node")
Reported-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds Broadcom SBA-RAID DT nodes for Stingray SoC.
The Stingray SoC has total 32 SBA-RAID FlexRM rings and it has
8 CPUs so we create 8 SBA-RAID instances (one for each CPU).
This way Linux DMAENGINE will have one SBA-RAID DMA device for
each CPU.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have two instances of FlexRM on Stingray. One for SBA RAID
offload engine and another for SPU2 Crypto offload engine.
This patch adds FlexRM mailbox controller DT nodes for Stingray.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add DT nodes for SATA host controllers and SATA PHYs
on Stingray SoC
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have 8 instances of sp804 in Stingray SoC. Let's enable
it in Stingray DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Added MDIO multiplexer iproc DT node for Stingray, which contains
the child nodes of PCIe serdes, RGMII, SATA and USB phy MDIO slaves.
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch enables stats for CCN-502 interconnect on Stingray.
Signed-off-by: Velibor Markovski <velibor.markovski@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
clock name of "audio_clkout" is used by Renesas sound driver.
This duplicated naming breaks its clock registering/unregistering.
Especially, when unbind/bind it can't handle clkout correctly.
This patch renames "audio_clkout" to "audio-clkout" to avoid
naming conflict.
Fixes: 8a8f181d2c ("arm64: renesas: salvator-x: use CS2000 as AUDIO_CLK_B")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for the rk3399 excavator main board.
This board works in a combination with the sapphire SOM.
This board have been sold as the rk3399 evaluation board for commercial customers.
You can get more info from below link:
http://opensource.rock-chips.com/wiki_Excavator_sapphire_board
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add support for the rk3399 sapphire SOM board.
This board works in a combination with the excavator main board.
You can get more info from below link:
http://opensource.rock-chips.com/wiki_Excavator_sapphire_board
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add an hdmi node, and also add hdmi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add an mipi node, and also add mipi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add an edp node, and also add edp endpoints to vopb and vopl
output port nodes.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
top level display-subsystem root node.
Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the
VOPs' output ports.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add opp tables for cpu cluster0 and cluster1 by including
rk3399-opp.dtsi.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
aliases node is identical for all boards, thus move it
to the common file ls208xa.dtsi.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Two fixes to correct the EMAC blocks memory region size to match the
datasheet. One that converts raw A83T clock indices to macros from the
clk dt-binding header, completing the A83T sunxi-ng clk driver.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAll566wOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDBBhw//RK8UpKhviq1kdn6yDNKe3dVYxRTGtISvpjJL
oPXpstt1b28DdbVjeIzh6jqF2HjjNmfFlLphOoOj1H7qKqhobr9+Cll05BNWbCmH
CIL6qL8FT7QyK8yw5sPLcdlNLkNil+KfgnrBf76Crdw0R1HXGENsw+gVE2lVX+tJ
yRqhguaQjWNLA5v+nfK4la+Ip1ddgKgiBmkpkq9tuR8hUDe33LHFZxur28EChHb/
P1HXL1DHUn2uO/tyk1TDhpYkNbOGiER4neOeQt21uaKLDaRMmkRlaNHgGg4CQ/fR
OYs24Sm0XB9oFVKzz2GttkIkdWTOqRI99VlXHEd3bU3Rc2PdClrdky615qkDn/90
CCjz7ibhnkri5+1/MWVC1iF/sotYnlCKjptXMZNRmqoyC2ol+tkNy84MoHvuWBCU
/IzCNuU8sGqC5/PjGNo2LwQNmzkFsk78s0MQAUyxG0isJwMrGQaSXGtOpSLJzUPv
MRBqYyK2CQk7gZtDyeZPepUUeQta/bAFIUROeozgTstvib86ywYrflrjkBTEyPar
Q+ptcoEgw1FVZZ4cQCGQWkg16dtFPSBMbGAbjlh/9DJXbZU/DVF5XRpTj8FthWm7
Vw/QQx4A18O+oS5/CkBjdltAb4RZIcF2ijAupRbwPIG+pzNVJVJ7JN7BzdVAFAyF
cf/Btkw=
=aFvT
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Pull "Allwinner fixes for 4.13" from Chen-Yu Tsai:
Two fixes to correct the EMAC blocks memory region size to match the
datasheet. One that converts raw A83T clock indices to macros from the
clk dt-binding header, completing the A83T sunxi-ng clk driver.
* tag 'sunxi-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros
arm64: allwinner: sun50i-a64: Correct emac register size
ARM: dts: sunxi: h3/h5: Correct emac register size
All the fixes are for ARM64 mvebu:
- Fix the RTC interrupt on A7K/A8K which was missed when switching
from GIC to ICU
- Mark the A7K/A8K crypto engine as dma coherent
- Fix the number of GPIO on south bridge on Armada 3700
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWYHbmCMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71ZhfAJ9Z9aMBG1xd
vbRYBDdqPdntruTudwCcDtM9jS2nL+207JfeMD0WMs7sDdU=
=XwFM
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu into fixes
Pull "mvebu fixes for 4.13 (part 2)" from Gregory CLEMENT:
All the fixes are for ARM64 mvebu:
- Fix the RTC interrupt on A7K/A8K which was missed when switching
from GIC to ICU
- Mark the A7K/A8K crypto engine as dma coherent
- Fix the number of GPIO on south bridge on Armada 3700
* tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
arm64: dts: marvell: mark the cp110 crypto engine as dma coherent
arm64: dts: marvell: use ICU for the CP110 slave RTC
- 2 minor DT fixes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJZf0PMAAoJEFk3GJrT+8ZlJskP/0JXcJt1I4myJv9A9z/+t0nh
7vT8H/ZwSyvK+/Iq1ccrf0Abe/c3445yHCwnF0T87R14A+oVVML5+uDolHIRZjlf
Wka34OoZFR9qTjphsFfQdZ0YcId7+a3BXNyvdkIWytWB+tzy/gpvlExBd54wJy0c
rceTEJsdmyObBFTmMTdlTzKQYLvurWoZ7d/N+T81UD3g0Xmq0EIOk0pEHSThK4SS
yQQWfRu7PCWDfXVu7qImalniaSa6wriHFC8hnrmaLfm2a9axfrTpvVknYuZUROlj
3T0Hgq3YHYe+BpS1P1Wryh60Yc8umbGy5JYg4GFOlNEGT9lBflk7nyG25aAbtwXY
BUU/r1cA1K+wR3XbUK9dpxW0GeCDTsQkHY9SA6+Aj5utNcMVhlnmGAHxJX9j1a8n
OhZtk339oCuBaf2Eg67OLvNGCPN21LAr2PL22LEGWkKSEUI61/1ZP1jjuCjN8Yk0
spXdFshdkYJyMqA4VuR05R5sBgqO25hXVDB2RYE4OuKINvAOfckgY9XpUhndxuYx
VVfX1up4bwoAUzVR+7XIsVrHaDR8pNS/Uv6kbhfB3X2c/jyPD1/Rc3T8p5DYirt7
DUPv8MJm/cwEC6uinQyqHTgB0tYLTWEY2+sv8NI2u8geYoJZO+Kt/12f3gcx296e
82LIlHnYKfYqUaqFwRRJ
=Z5d3
-----END PGP SIGNATURE-----
Merge tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into fixes
Pull "Amlogic fixes for v4.13-rc" from Kevin Hilman:
- 2 minor DT fixes
* tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: meson-gxl-s905x-libretech-cc: fixup board definition
ARM64: dts: meson-gx: use specific compatible for the AO pwms
The ESPRESSObin board exposes one of the SDHCI interfaces
via J1 uSD slot. This patch enables it.
Tested-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Zbigniew Bodek <zbodek@gmail.com>
[gregory.clement@free-electrons.com: removed "no-1-8-v"]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Since the introduction of the CP110 dt files, the sata node was
misplaced. Move it at the right place. Thanks to this, the files are
completely ordered.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
In both the CP110 master and slave description, the node describing
the RTC was at the wrong place when taking into account increasing
register addresses. Interestingly, it was not even at the same (wrong)
place in both files.
This commit adjusts that, making the master and slave descriptions
more aligned.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch adds an stdout-path to the mcbin device tree. This allows to
use earlycon.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add support for PCIe with the the PCIe reset signal wired up to the
appropriate GPIO pin.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
(excepted the reset part)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The MACCHIATOBin board has a PCA9548 I2C mux for the SFP ports on
CP100 master I2C bus 1. Add the DT description for it.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Due to the lack of GPIO support, the USB3 regulator definition was
left unfinished in the MacchiatoBin DT description. Now that GPIO
support is available, this commit adjusts the Device Tree to properly
describe the USB3 regulator.
[gregory.clement@free-electrons.com: use commit log from Thomas]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add pinctrl nodes to describe the CPM I2C0 and CPS SPI1 settings.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the GPIO interrupts for the CP110.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Espressobin SBC has a USB2 interface available on J8. Let's
enable it.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.
Advertise the PMUv3 presence in the device tree, and wire its
interrupt. This allows the perf subsystem to work correctly.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.
Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The GIC-500 integrated in the Armada-37xx SoCs is compliant with
the GICv3 architecture, and thus provides a maintenance interrupt
that is required for hypervisors to function correctly.
With the interrupt provided in the DT, KVM now works as it should.
Tested on an Espressobin system.
Fixes: adbc3695d9 ("arm64: dts: add the Marvell Armada 3700 family and
a development board")
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Fixes: afda007fed ("ARM64: dts: marvell: Add pinctrl nodes for Armada
3700")
Cc: <stable@vger.kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Since underscores('_') are not allowed in the device tree nodes names,
replace all of them with hyphen('-') in device node names. Note that
underscores are however allowed in labels.
Reported-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Use the new compatible for ATB programmable replicator in Juno.
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This patch describes the GPIO lines usage on the Nanopi K2 board.
This is useful in the debugfs gpio file and using the cdev gpio API.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch describes the GPIO lines usage on the Khadas VIM board.
This is useful in the debugfs gpio file and using the cdev gpio API.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: minor whitespace fix]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Changing the card voltage on the p200 is not instantaneous, especially
when switching from 3.3v to 1.8v.
I take at least 70ms for the regulator to go from 3.3v to 1.8v. Add
margin to that to make sure we don't upset the sdcard during the voltage
switch
Fixes: ef8d2ffedf ("ARM64: dts: meson-gxbb: add MMC support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch updates the dynamic-power-coefficient for big cluster on
rk3399 SoCs.
The dynamic power consumption of the CPU is proportional to the square of
the Voltage (V) and the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
Where Voltage is in uV, frequency is in MHz.
As the following is the tested data on rk3399's big cluster.
frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient
24 0.8 15
48 0.8 23 ~417
96 0.8 40 ~443
216 0.8 82 ~438
312 0.8 115 ~430
408 0.8 150 ~455
So the dynamic-power-coefficient average value is about 436.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
BCM2837 is somewhat unusual in that we build its DT on both arm32 and
arm64. Most devices are being run in arm32 mode.
Having the body of the DT for 2837 separate from 2835/6 has been a
source of pain, as we often need to make changes that span both
directories simultaneously (for example, the thermal changes for 4.13,
or anything that changes the name of a node referenced by '&' from
board files). Other changes are made more complicated than they need
to be, such as the SDHOST enabling, because we have to split a single
logical change into a 283[56] half and a 2837 half.
To fix this, make the stub board include file live in arm64 instead of
arm32, and keep all of BCM283x's contents in arm32. From here on, our
changes to DT contents can be submitted through a single tree.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Place northstar2 into its own subdirectory. This helps as the number
of Broadcom boards grow and we can separate them per SoC.
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add node for the Amlogic Meson GX SoC information register.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds support for hsusb ch3 device nodes for R-Car H3 ES2.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds support for usb-dmac ch2 and ch3 device nodes for
R-Car H3 ES2.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds support for usb2.0 host ch3 device nodes for R-Car
H3 ES2.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds support for usb3_phy ch3 device node for R-Car H3 ES2.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the "companion" property in the EHCI ch0, ch1 and
ch2 nodes to wait for the usb companion controller startup at resume.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[remove ch3 node and revise the commit log]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Basic support for the Renesas Draak board based on R-Car D3:
- Memory,
- Main crystal,
- Serial console,
- Watchdog.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DU dot clocks 0 and 3 are provided by the programmable VC6 clock
generator. Connect them to the clock source node.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The VC6 is an I2C-controlled programmable clock generator, used on the
board to provide a display dot clock. Add it to DT.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of
DMA specifiers. However, the second pair of corresponding DMA names was
missing.
Fixes: 80fab06e25 ("arm64: dts: r8a7796: Add all MSIOF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domain, dma, and reset properties.
Due to a hardware erratum on R-Car H3 ES1.x, using MSIOF for SPI is only
supported on ES2.0 and later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a compatible string and VSP links to the DU node. The H3 ES1.x and
H3 ES2.0 are compatible save for the links to the VSPs that are
described explicitly in DT, so there's no need for a new ES2-specific
compatible string.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable the HDMI encoder for ULCB board and hook it up to the HDMI connector.
The HDMI encoder and connector are available on both the H3 and M3-W ULCB boards.
Add them to the ulcb.dtsi file.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The ULCB board has one HDMI output connector.
This connector is available on both the H3 and M3-W ULCB boards.
Add this to the ulcb.dtsi file.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DU0/DU1/DU2 external dot clocks are provided by the programmable
Versaclock5 clock generator.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DU0/DU1/DU2/DU3 external dot clocks are provided by the programmable
Versaclock5 clock generator.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DU0/DU1/DU2/DU3 external dot clocks are generated by an I2C-controlled
programmable clock generator.
Clock generator is available on both the H3 and M3-W ULCB boards.
Add this to the ulcb.dtsi file.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable the HDMI encoder for the M3-W Salvator-X board and hook it up to
the HDMI connector.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DU1 external dot clock is provided by the fixed frequency clock
generator X21, while the DU0 and DU2 clocks are provided by the
programmable Versaclock5 clock generator.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the HDMI encoder to the R8A7796 DT in disabled state.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the DU device to r8a7796.dtsi in a disabled state.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The FCPs handle the interface between various IP cores and memory. Add
the instances related to the FDPs and VSP2s.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables I2C4 for ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables I2C for DVFS device for ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The definition of CPG_AUDIO_CLK_I is SoC-specific, not board-specific.
Hence move it from the board-specific .dts files to the SoC-specific
.dtsi files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the IMR-LX4 devices in the R8A7796 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the IMR-LX4 devices in the R8A7795 device tree.
Based on the original (and large) patch by Konstantin Kozhevnikov
<Konstantin.Kozhevnikov@cogentembedded.com>.
Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The datasheet said that emac register size is 0x10000 not 0x100
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Fixed commit subject prefix]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Correct order of sound clock frequencies for ULCB boards
used by r8a7795 and r8a7796 SoCs.
These sounds clock frequencies are used as the ADG clock (output clocks
for audio module) initial setting and sound codec's initial system clock
which needs the maximum clock frequency. Thus, descending order is
required.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZaHmuAAoJENfPZGlqN0++XmQP/i7HumkEn4LPeyEQ/ePTwOHs
zz6CNekfmW0aJe4lceRmZ/xMkIuzrwma+EsQj3xj35cl1iK3MvjkguVYAFeYVhJb
w0X0qJp/0Opz0RNlKo4Pufj0yWy1ZyAQ9ci3UZELTik1sJI/7LG9eyjrXfaxRywo
OrYq3l41t9Y3/5e9MThUP4oxLO5B8YaJDtGGVYOoVk7cIs0PM9ffG8GVz0IPbrmF
wFEbVr/EohjpQL0SJ5GO2+NJhUbJFRuLOBWZOTyBQiZ3GByloRXzDR6gU/XSczHB
vElss4KZiWp2k7xRaBgaHK88u8wSOKdDkXrl6pto+aw1gAlFtOgWArKNQtkrp0vd
+VHk7Emhdnsw9SWTz0N+Oq7fyA2QIWo1sBr16AkmgB/JStlOXklJWjKgtyK0+mLj
FZAhOz5qO9ctr0WO87gbVvTz9xcs81g/K0D9rFTlmEIF8GEuDZxrX43LlIDl7I9r
nbfBj/HFtXqQXLIzS2OR9ah2F5DFWMym2/+mYuSkOt883PrbyjBq2xNdDD+QYcnO
+p6xCHAY/xiT953NBs/2z0kAXp6bWMjEOO7Lsv3SnPUss7Nng6RU2wbJepZd05Lo
ZH0k1L7IJtq2UVduHFYkEwKzTGCycW4mmposVNHZm42FOw19nR6Xd3khU57fMAni
ZH59p+Q/lFxcddwDZ0T1
=bjUb
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes2-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Second Round of Renesas ARM Based SoC Fixes for v4.13" from Simon Horman:
Correct order of sound clock frequencies for ULCB boards
used by r8a7795 and r8a7796 SoCs.
These sounds clock frequencies are used as the ADG clock (output clocks
for audio module) initial setting and sound codec's initial system clock
which needs the maximum clock frequency. Thus, descending order is
required.
* tag 'renesas-fixes2-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: renesas: ulcb: sound clock-frequency needs descending order
Correct order of sound clock frequencies for Salvator boards
used by r8a7795 and r8a7796 SoCs.
These sounds clock frequencies are used as the ADG clock (output clocks
for audio module) initial setting and sound codec's initial system clock
which needs the maximum clock frequency. Thus, descending order is
required.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZVhaCAAoJENfPZGlqN0++/zkP/1aHxFA560O3cb4SebIeJKQd
TQFd7YocK1lsqD6DP1ZLQI7ytPfpyAKPctKLRe2NSwr+kf5N8rbYUfZ88pBXe7ez
y9mbFBYcKHvDLrGHtW5hebBGB6HAh2Ll9DMW6Hqdsv8qG1/EqlLwBkA10/VSjaYk
Xfp4XnbyXsWCxbllU04We0uel945rg6tQy6VBszW5QEwMEX4zhaOsmi6z8nCv11E
k8Q6xl2/+FWc/zfivJSzBn59XjQSo+E54yRkmaYcteTY2+8Y787QMvVKkbUAvnHi
DrVplSPdbQPeZInqDiw97fvUNDTIzYatskMF3Lv6HFZ+u8YHTrW6yq2CShWtecUx
7BP8GgwfkLHt8J5PADMpNejzfE5lz+7EPm8+2jhGeoHd0BNjojaFvbyL01pJntwp
nJrSKlLmRB1CDEiubVPUUrY+EWcx7wxK0V8eliWTAn/o1ijJTErbRF91Z/U9BACF
PQUToBZ8MJKbjbrFXmelswkTwORV7au0KwY6Jzm2Vue7TiCZU4BXwyxZ1hmH3dI1
GLOWo5mtlXWcUnHLrPv44x6povNQDCtPGowTyKkqo2vXIAlAkMaG4V5D2tV9ykr7
d0UDWA44fF7QYcgW8hEd1eY0ILnYuX7Zanh0xvb5OBjqLEwsf+FvLel6/eMzg4Pj
tNB+iosh5YumUfCIue0D
=t800
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Renesas ARM Based SoC Fixes for v4.13" from Simon Horman:
Correct order of sound clock frequencies for Salvator boards
used by r8a7795 and r8a7796 SoCs.
These sounds clock frequencies are used as the ADG clock (output clocks
for audio module) initial setting and sound codec's initial system clock
which needs the maximum clock frequency. Thus, descending order is
required.
* tag 'renesas-fixes-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: renesas: salvator-common: sound clock-frequency needs descending order
This allows basic support for SD highspeed cards but no UHS-I mode
got ready due to the propagated defer-probe error from RK805.
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the core grf subnode for the io-domain controller.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
LS1012A has one USB 3.0(DWC3) controller and
one USB 2.0 controller.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64
SoC, and the regulators of the PMIC are used both on the SoM itself and
on the official baseboard
Add related device tree parts to the SoPine SoM DTSI file and the
baseboard DT.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add support of AXP803 regulators in the Pine64 device tree.
The phy-supply regulator is also set in EMAC device node, in order to
prevent Ethernet regression by regulator get disabled by regulator
framework.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Kill these two pinctrl reference totally from rk3399 as it
never work indeed.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pcie_clkreqn actually doesn't work at all, so replace it with
pcie_clkreqn_cpm.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
keep-power-in-suspend was invented for SDIO only, so it should
not be used for eMMC node.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
the mailbox and ethmac nodes used the magic number "0" instead of the
GIC_SPI preprocessor macro. Additionally the ethmac used the magic
number "1" instead of IRQ_TYPE_EDGE_RISING.
Fix this to make the .dtsi easier to read.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The libretech CC derives less from the p212 than initially thought.
Several voltage regulators are different and the capabilities of the
sdcard and emmc also differ.
Deriving from the p212 is not convient anymore so the libretech is now
derived from s905x definition directly.
Fixes: cd84aff1d9 ("ARM64: dts: meson-gxl: Add Libre Technology CC support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Use the specific compatible for AO pwms so the pwms input can
be correctly set
FDIV4 is not present on the pwm A0, so change kadhas vim input
clocks to xtal.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Warnings:
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the support for the MT7622 reference board variant 1 from
MediaTek.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
add basic nodes into the mt7622.dtsi for the system
bring-up which includes ARM CPU, GIC, timer, MediaTek
UART, SYSIRQ and one reserved memory region for ATF.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The crypto engines found on the cp110 master and slave are dma coherent.
This patch adds the relevant property to their dt nodes.
Cc: stable@vger.kernel.org # v4.12+
Fixes: 973020fd94 ("arm64: marvell: dts: add crypto engine description for 7k/8k")
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
When the conversion of the Marvell CP110 Device Tree description from
using GIC interrupts to using ICU interrupts was done, the RTC on the
slave CP110 was left unchanged. This commit fixes that, so that all
devices on the CP properly get their interrupt through the ICU.
Fixes: 6ef84a827c ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
dwmmc driver deprecated num-slots and plan to get rid
of it finally. Just move a step to cleanup it from DT.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Since commit 9840354ff4 ("usb: dwc3: Add dual-role support") dwc3
node requires extcon property to be initialized as OTG mode and it
supports dual-role mode operation.
Signed-off-by: Dongwoo Lee <dwoo08.lee@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Exynos5433 has two usb 3.0 controllers: usbhost and usbdrd. usbhost
is host-only controller whereas usbdrd supports both peripheral and
host mode. "drd" means dual-role device, so usbhost cannot be labeled
with the name containing "drd". However, the label usbdrd_dwc3_0 was
used for usbhost's dwc3 node. It seems it obviously fault because TM2
and TM2E doesn't use usbhost but dr_mode property is assigned to it.
This patch assigns the proper label for two dwc3 nodes.
Signed-off-by: Dongwoo Lee <dwoo08.lee@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The OF graph is not needed because the panel is a child of dsi. Remove
the ports node in DSI node.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[wens@csie.org: Add fallback sun6i-a31-r-intc compatible]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We deprecated the "num-slots" property now and plan to get
rid of it finally. Just move a step to cleanup it from DT.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pcie_clkreqn actually doesn't work at all, so replace it with
pcie_clkreqn_cpm.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The SdioAudio power domain includes the i2s/spdif/spi5/sdio.
So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order
to save more power consumption.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip's RK3328 evaluation board has one usb2 otg controller
and one usb2 host controller which consist of EHCI and OHCI.
Each usb controller connects with one usb2 phy port through
UTMI+ interface. Let's enable them to support usb2 on RK3328
evaluation board.
Signed-off-by: William Wu <william.wu@rock-chips.com>
[restructured enablement of u2phy subnodes]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Provide the dynamic power coefficient of the big and little CPU
clusters. These numbers are currently in use on the Samsung Chromebook
Plus ("Kevin").
The power allocator thermal governor doesn't know how to do anything if
it doesn't get power parameters from its cooling devices (in this case,
CPUfreq). So this effectively enables the power-allocator governor.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[set the property in each core node]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Gru device tree currently contains entries for the regulators
ppvar_bigcpu, ppvar_litcpu, ppvar_gpu and ppvar_centerlogic; however,
the regulators have not been enabled, due to the lack of binding and driver
support for keeping the over-voltage protection (OVP) at bay and
preventing unintended regulator shutdowns on voltage downshifts.
Now, the vctrl regulator driver has been merged, along with new bindings
for asymmetric settling time. The driver is OVP aware, it splits larger
voltage decreases in multiple steps when necessary and adds required
delays.
This change renames each of the aforementioned regulators to
<orig_name>_pwm and adds a new vctrl regulator named <orig_name>.
The vctrl regulators use the voltage of their corresponding PWM regulator
as control voltage. The OVP related values are empirical and stem from
the Chrome OS kernel tree.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
[fixed node names and parent supplies of gpu and centerlogic]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Gru derivatives besides Kevin have slightly different voltage ranges for
their CPU regulators. Let's keep the base Gru file accurate and let
Kevin override.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
replace all occurrences of sdmcc with sdmmc in the arm64 rockchip
devicetree files.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add nodes of watchdog timer for UniPhier LD11 and LD20 SoC.
The watchdog timer is included in sysctrl.
Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
dwmmc driver deprecated num-slots and plan to get rid
of it finally. Just move a step to cleanup it from DT.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Correct order of sound clock frequencies for ULCB boards
used with r8a7795 and r8a7796 SoCs.
These sounds clock frequencies are used as the ADG clock (output clocks
for audio module) initial setting and sound codec's initial system clock
which needs the maximum clock frequency. Thus, descending order is
required.
Fixes: 9f22774c21 ("arm64: dts: ulcb: add 12288000 for sound ADG")
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: rewrote changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pull networking updates from David Miller:
"Reasonably busy this cycle, but perhaps not as busy as in the 4.12
merge window:
1) Several optimizations for UDP processing under high load from
Paolo Abeni.
2) Support pacing internally in TCP when using the sch_fq packet
scheduler for this is not practical. From Eric Dumazet.
3) Support mutliple filter chains per qdisc, from Jiri Pirko.
4) Move to 1ms TCP timestamp clock, from Eric Dumazet.
5) Add batch dequeueing to vhost_net, from Jason Wang.
6) Flesh out more completely SCTP checksum offload support, from
Davide Caratti.
7) More plumbing of extended netlink ACKs, from David Ahern, Pablo
Neira Ayuso, and Matthias Schiffer.
8) Add devlink support to nfp driver, from Simon Horman.
9) Add RTM_F_FIB_MATCH flag to RTM_GETROUTE queries, from Roopa
Prabhu.
10) Add stack depth tracking to BPF verifier and use this information
in the various eBPF JITs. From Alexei Starovoitov.
11) Support XDP on qed device VFs, from Yuval Mintz.
12) Introduce BPF PROG ID for better introspection of installed BPF
programs. From Martin KaFai Lau.
13) Add bpf_set_hash helper for TC bpf programs, from Daniel Borkmann.
14) For loads, allow narrower accesses in bpf verifier checking, from
Yonghong Song.
15) Support MIPS in the BPF selftests and samples infrastructure, the
MIPS eBPF JIT will be merged in via the MIPS GIT tree. From David
Daney.
16) Support kernel based TLS, from Dave Watson and others.
17) Remove completely DST garbage collection, from Wei Wang.
18) Allow installing TCP MD5 rules using prefixes, from Ivan
Delalande.
19) Add XDP support to Intel i40e driver, from Björn Töpel
20) Add support for TC flower offload in nfp driver, from Simon
Horman, Pieter Jansen van Vuuren, Benjamin LaHaise, Jakub
Kicinski, and Bert van Leeuwen.
21) IPSEC offloading support in mlx5, from Ilan Tayari.
22) Add HW PTP support to macb driver, from Rafal Ozieblo.
23) Networking refcount_t conversions, From Elena Reshetova.
24) Add sock_ops support to BPF, from Lawrence Brako. This is useful
for tuning the TCP sockopt settings of a group of applications,
currently via CGROUPs"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1899 commits)
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
dt-bindings: phy: dp83867: provide a workaround for incorrect RX_CTRL pin strap
cxgb4: Support for get_ts_info ethtool method
cxgb4: Add PTP Hardware Clock (PHC) support
cxgb4: time stamping interface for PTP
nfp: default to chained metadata prepend format
nfp: remove legacy MAC address lookup
nfp: improve order of interfaces in breakout mode
net: macb: remove extraneous return when MACB_EXT_DESC is defined
bpf: add missing break in for the TCP_BPF_SNDCWND_CLAMP case
bpf: fix return in load_bpf_file
mpls: fix rtm policy in mpls_getroute
net, ax25: convert ax25_cb.refcount from atomic_t to refcount_t
net, ax25: convert ax25_route.refcount from atomic_t to refcount_t
net, ax25: convert ax25_uid_assoc.refcount from atomic_t to refcount_t
net, sctp: convert sctp_ep_common.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_transport.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_chunk.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_datamsg.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_auth_bytes.refcnt from atomic_t to refcount_t
...
Device-tree updates for arm64 platforms. For the first time I can
remember, this is actually larger than the corresponding branch for
32-bit platforms overall, though that has more individual changes.
A significant portion this time is due to added machine support:
- Initial support for the Realtek RTD1295 SoC, along with the Zidoo
X9S set-top-box
- Initial support for Actions Semi S900 and the Bubblegum-96
single-board-cёmputer.
- Rockchips support for the rk3399-Firefly single-board-computer
gets added, this one stands out for being relatively fast,
affordable and well₋supported, compared to many boards that
only fall into one or two of the above categories.
- Mediatek gains support for the mt6797 mobile-phone SoC platform
and corresponding evaluation board.
- Amlogic board support gets added for the NanoPi K2 and S905x
LibreTech CC single-board computers and the R-Box Pro set-top-box
- Allwinner board support gets added for the OrangePi Win,
Orangepi Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single
board computers and the SoPine system-on-module.
- Renesas board support for Salvator-XS and H3ULCB
automotive development systems.
- Socionext Uniphier board support for LD11-global and LD20-global,
whatever those may be.
- Broadcom adds support for the new Stingray communication processor
in its iProc family, along with two reference boards.
Other updates include:
- For the hisicon platform, support for Hi3660-Hikey960 gets
extended significantly.
- Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAWVpZnmCrR//JCVInAQJYsBAAhuoRK5WZawkeAMEbkGeyOXYbnp6qUlKm
w1lwXXdStLjkOUmQXo5KNDmWiHbPnuhwHprX9HMPDI0G1+DSaOlxIezNFIlKOUyW
fQxZjt4+L3eRXQCetj3P+QAp37ifmFxSg0RmM+fGBwAhNcyf6nH98cn4ZaauZrfu
F3cJz9t9MTdIlxXXF1uTAk9g9tR8sCoD4ekmM15MwtLZZTqmZNP1OelRDwwzNoOn
6pp4BUDOFhesynsI7uYoKdj0lt0fGg348FAlt9w1g9xQ819wrdaz/eAmV49eUZQ+
Ps8FY1OvJsVaoe3yGeEG0Ps87VTRCzSOFqstNDftYsz+q5Mm8ImEwG8JhuoqyDQD
/VW+DamdXyN4tuUFQfg+Cz8+6WZRwfTeOVmuvC4aRuKNDWV5CC5qP1B7oZ/a2nYR
6M8+1W+RJOgjJ9wa/125Z6edEpzCRzfxDSLKyHbQ2q//0NK0kRrS9+Rdi6FlReV3
mVGtK5gFLVzcCyBSaMY48KnRe0/cjOZ5YXw5o/DIeYJkyPnOlN1pXOEMalQCf+uI
6D8pjO307lt6TLCiq3i2C8bN5k0FBqD4rirsp9PlRw3vTx1LI+KnhJQ8NOrrTheW
gtDevoDMssnJdmVj3Wbv8DPWJOGSF6vA/xvsQBe0MglHFtuR/0jp9YC8ncvIP1RC
CkFTqmpZXYg=
=E8pa
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"Device-tree updates for arm64 platforms. For the first time I can
remember, this is actually larger than the corresponding branch for
32-bit platforms overall, though that has more individual changes.
A significant portion this time is due to added machine support:
- Initial support for the Realtek RTD1295 SoC, along with the Zidoo
X9S set-top-box
- Initial support for Actions Semi S900 and the Bubblegum-96
single-board-cёmputer.
- Rockchips support for the rk3399-Firefly single-board-computer gets
added, this one stands out for being relatively fast, affordable
and well₋supported, compared to many boards that only fall into one
or two of the above categories.
- Mediatek gains support for the mt6797 mobile-phone SoC platform and
corresponding evaluation board.
- Amlogic board support gets added for the NanoPi K2 and S905x
LibreTech CC single-board computers and the R-Box Pro set-top-box
- Allwinner board support gets added for the OrangePi Win, Orangepi
Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers
and the SoPine system-on-module.
- Renesas board support for Salvator-XS and H3ULCB automotive
development systems.
- Socionext Uniphier board support for LD11-global and LD20-global,
whatever those may be.
- Broadcom adds support for the new Stingray communication processor
in its iProc family, along with two reference boards.
Other updates include:
- For the hisicon platform, support for Hi3660-Hikey960 gets extended
significantly.
- Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits)
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
arm64: dts: mediatek: don't include missing file
ARM64: dts: meson-gxl: Add Libre Technology CC support
dt-bindings: arm: amlogic: Add Libre Technology CC board
dt-bindings: add Libre Technology vendor prefix
arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
arm64: dts: zte: Use - instead of @ for DT OPP entries
arm64: dts: marvell: add gpio support for Armada 7K/8K
arm64: dts: marvell: add pinctrl support for Armada 7K/8K
arm64: dts: marvell: use new binding for the system controller on cp110
arm64: dts: marvell: remove *-clock-output-names on cp110
arm64: dts: marvell: use new bindings for xor clocks on ap806
arm64: dts: marvell: mcbin: enable the mdio node
arm64: dts: Add Actions Semi S900 and Bubblegum-96
dt-bindings: Add vendor prefix for uCRobotics
arm64: dts: marvell: add xmdio nodes for 7k/8k
arm64: dts: marvell: add a comment on the cp110 slave node status
arm64: dts: marvell: remove cpm crypto nodes from dts files
arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
...
Here is the "big" char/misc driver patchset for 4.13-rc1.
Lots of stuff in here, a large thunderbolt update, w1 driver header
reorg, the new mux driver subsystem, google firmware driver updates, and
a raft of other smaller things. Full details in the shortlog.
All of these have been in linux-next for a while with the only reported
issue being a merge problem with this tree and the jc-docs tree in the
w1 documentation area. The fix should be obvious for what to do when it
happens, if not, we can send a follow-up patch for it afterward.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCWVpXKA8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ynLrQCdG9SxRjAbOd6pT9Fr2NAzpUG84YsAoLw+I3iO
EMi60UXWqAFJbtVMS9Aj
=yrSq
-----END PGP SIGNATURE-----
Merge tag 'char-misc-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc updates from Greg KH:
"Here is the "big" char/misc driver patchset for 4.13-rc1.
Lots of stuff in here, a large thunderbolt update, w1 driver header
reorg, the new mux driver subsystem, google firmware driver updates,
and a raft of other smaller things. Full details in the shortlog.
All of these have been in linux-next for a while with the only
reported issue being a merge problem with this tree and the jc-docs
tree in the w1 documentation area"
* tag 'char-misc-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (147 commits)
misc: apds990x: Use sysfs_match_string() helper
mei: drop unreachable code in mei_start
mei: validate the message header only in first fragment.
DocBook: w1: Update W1 file locations and names in DocBook
mux: adg792a: always require I2C support
nvmem: rockchip-efuse: add support for rk322x-efuse
nvmem: core: add locking to nvmem_find_cell
nvmem: core: Call put_device() in nvmem_unregister()
nvmem: core: fix leaks on registration errors
nvmem: correct Broadcom OTP controller driver writes
w1: Add subsystem kernel public interface
drivers/fsi: Add module license to core driver
drivers/fsi: Use asynchronous slave mode
drivers/fsi: Add hub master support
drivers/fsi: Add SCOM FSI client device driver
drivers/fsi/gpio: Add tracepoints for GPIO master
drivers/fsi: Add GPIO based FSI master
drivers/fsi: Document FSI master sysfs files in ABI
drivers/fsi: Add error handling for slave
drivers/fsi: Add tracepoints for low-level operations
...
It is actually a patch that missed the end of the 4.12 merge
window. The patch itself fix a bogus definition of the timer for the
Armada 37xx SoCs.
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWVpGxCMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71SGMAKCP9mGjMWqD
Z9uCT8swDJ8LCi/o+wCfV4Cs0eWzqkJUDMaycdJrlMjB174=
=TavE
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.13-3' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "late dt64 for 4.13" from Gregory CLEMENT:
It is actually a patch that missed the end of the 4.12 merge
window. The patch itself fix a bogus definition of the timer for the
Armada 37xx SoCs.
* tag 'mvebu-dt64-4.13-3' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Contrary to popular belief, PPIs connected to a GICv3 to not have
an affinity field similar to that of GICv2. That is consistent
with the fact that GICv3 is designed to accomodate thousands of
CPUs, and fitting them as a bitmap in a byte is... difficult.
Fixes: adbc3695d9 ("arm64: dts: add the Marvell Armada 3700 family and
a development board")
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This reverts commits 2c0cba482e ("arm: sun8i: sunxi-h3-h5: Add dt node
for the syscon control module") to 2428fd0fe5 ("arm64: defconfig: Enable
dwmac-sun8i driver on defconfig") and 3432a86e64 ("arm: sun8i:
orangepipc: use internal phy-mode") to 5a79b4f2a5 ("arm: sun8i:
orangepi-2: use internal phy-mode") that should be merged
through the arm-soc tree, and end up in merge conflicts and build failures.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This adds an initial DT for the S900 SoC and a devboard based on it.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJZTULJAAoJEPou0S0+fgE/00gP/3V47/jMZmIcRZymiRXUkZAc
cZiIkeKXa0LEXQPk5iTAVXCU7vfhWHHq3g9lA+CWMhbBKO+6K/RwipdscqAxLNfF
kaIIO4M1CEVB9R55JR2jTd6qEHBD+MibTxYc2bbfrWJtbaQJWZ+ep0oKqpOccoby
BRb5yhBt0b0K4GOlgOQHNVIc6sbdhH8ZJ+n/Dqj57eDxzH/u+DUaWdwAIHDaN8Qw
+qAM4HTYSXnlwjWgRgeBws7adDV8wDLbQwpNrmHjDBGxZ8BTIZxrnydKG7AUMIPi
o8A50c7khq4xFQN+IhhNrhwQpilMRjlZc84DwqBsFdaUzei4jYZmY8udxKyuJdhr
ZMerSnvoBOew/KpyvhxaT0aHD0Zlxzl6yKy7dw3FAbqnQTUUmpwp2kM1bsNteMwU
FD5YvLv04R8y9w8XJdsPATQiqu06dZIBZdHubI4D3hWMMYi963eH7KE9ON8mq5Uc
d7Ex1+q9DvjiwOlPtTAcLoeAQeVKeojrDQTTpH4GR3PtukJVBLzS1IiFl1qweele
G1i0WTUgSuYmlvoWOIX4jzeejiXab5WOUszdsIT5qx0LIZKnS/XfQe/kjOYcto6Z
3244hW7AXkdVGOieUX4d+DiizlvJe6VPbq5RJ6Ka5ZmWIdUbH5KkDT4F/jSoi4d4
Ny4hC2twmGfmUIFqbBpp
=WMGS
-----END PGP SIGNATURE-----
Merge tag 'actions-arm64-dt-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt64
Pull "Actions Semi ARM64 based SoC DT for 4.13" from Andreas Färber:
This adds an initial DT for the S900 SoC and a devboard based on it.
* tag 'actions-arm64-dt-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
arm64: dts: Add Actions Semi S900 and Bubblegum-96
dt-bindings: Add vendor prefix for uCRobotics
As I found by chance while merging another patch, the usage of
a dma-mask in this DT node is wrong for multiple reasons:
- dma-masks are a Linux specific concept, not a general
hardware feature
- In DT, we use the "dma-ranges" property to describe how DMA
addresses related between devices.
- The 40-bit mask appears to be completely unnecessary here, as
the SoC cannot address that much memory anyway, so simply
asking for a 64-bit mask (as supported by the device) should
succeed anyway.
The patch to remove the parsing of the property is getting merged
through the crypto tree.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix the interrupt description of the crypto node for device tree of
the Armada 7K/8K SoCs
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWTAszCMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71bcsAJ4kcIDc5FwI
e9qfRomziu3A+S6K0QCfX3Ii7XGH1fANfeTCAnyZGXmYFZI=
=wjTT
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu fixes for 4.12
Fix the interrupt description of the crypto node for device tree of
the Armada 7K/8K SoCs
* tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes
- use new clock binding for Armada 7K/8K
- add pinctrl on Armada 7K/8K
- add GPIO on Armada 7K/8K
- switch from GIC to ICU on CP110 (Armada 7K/8K)
- enable the mdio node on the mcbin (Armada 8K based board)
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWUu1OyMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71eSWAJoCt4L+K8aB
pXG1iuqtFCBtgXXfMQCgi/jFA0Qbq8oInY1qYmE44SG1fhY=
=0hb0
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.13 (part 2)" from Gregory CLEMENT:
- use new clock binding for Armada 7K/8K
- add pinctrl on Armada 7K/8K
- add GPIO on Armada 7K/8K
- switch from GIC to ICU on CP110 (Armada 7K/8K)
- enable the mdio node on the mcbin (Armada 8K based board)
* tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
arm64: dts: marvell: add gpio support for Armada 7K/8K
arm64: dts: marvell: add pinctrl support for Armada 7K/8K
arm64: dts: marvell: use new binding for the system controller on cp110
arm64: dts: marvell: remove *-clock-output-names on cp110
arm64: dts: marvell: use new bindings for xor clocks on ap806
arm64: dts: marvell: mcbin: enable the mdio node
- Fix DTC unit_address_vs_reg warnings in OPP entries by replacing
'@' with '-' as the OPP nodes will never have a "reg" property.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJZSlgkAAoJEFBXWFqHsHzOxVsIALRBWPPcnJBNafvKxtL+DH63
9lt62gZwKzLerqPVchGvapHfvpS5tu19fmmlvYIDZIICD4hjPQgdSN9EmKjGkhdo
sIpBqJgYZ6i7OJEJMNKEUaDPqLXJY9Q2DVVVwIudtNnIu5EPYlCrQuGjQ5l2SXfk
HeSeIOfybCbQM67fe2hP1Uk9P4AeVs+grTyg4nH3qP4kgEnd5fLkdNPdF2NGytE9
IdzykK6LFDzDDW4qFL8T8luJpzh3gEsy2ecXpoI3WyCpdaZvIrFgXtvoFzdBTKBX
4MQEnwaBn5OscAnXXGRzyPOsovSC6o6lkLCNw97ZwEbZGG4HdorhW8RGqqPm0yU=
=/6Fg
-----END PGP SIGNATURE-----
Merge tag 'zte-dt64-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Pull "ZTE arm64 device tree updates for 4.13" from Shawn Guo:
- Fix DTC unit_address_vs_reg warnings in OPP entries by replacing
'@' with '-' as the OPP nodes will never have a "reg" property.
* tag 'zte-dt64-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zte: Use - instead of @ for DT OPP entries
This resolves a build error in the next/dt branch:
In file included from arch/arm64/boot/dts/mediatek/mt6797-evb.dts:16:0:
arch/arm64/boot/dts/mediatek/mt6797.dtsi:15:10: fatal error: dt-bindings/power/mt6797-power.h: No such file or directory
003f5d0c34 ("arm64: dts: mediatek: add clk and scp nodes for MT6797")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add support for the CC board from Shenzhen Libre Technology
More information about the board are available here:
https://libre.computer/blog/
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Two entries being added at the same time to the IFLA
policy table, whilst parallel bug fixes to decnet
routing dst handling overlapping with the dst gc removal
in net-next.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
The Armada 8K has two CP110 blocks, each having two GPIO controllers.
However, in each CP110 block, one of the GPIO controller cannot be
used: in the master CP110, only the second GPIO controller can be used,
while on the slave CP110, only the first GPIO controller can be used.
On the other side, the Armada 7K has only one CP110, but both its GPIO
controllers can be used.
For this reason, the GPIO controllers are marked as "disabled" in the
armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
enabled in the per-SoC dtsi files.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.
These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The new binding for the system controller on cp110 moved the clock
controller into a subnode. This preliminary step will allow to add gpio
and pinctrl subnodes.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The *-clock-output-names of the cp110-system-controller0 node are not
used anymore, so remove them.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
New bindings are used for the system controller on the ap806, which
means all clock properties must be converted. Use the new bindings in
the xor nodes.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Since the mdio nodes are disabled by default now, we should explicitly
enable these nodes at the board level when they are used. Enable the
cpm_mdio node for the 8040-mcbin.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
It will be used ADG clock initial settings, and will be
sound codec's initial system clock which needs maximum clock frequency.
Thus, descending order is required
Fixes: d37d2b3c0e ("arm64: dts: salvator-x: add 12288000 for sound ADG")
Fixes: 0b03c32db0 ("arm64: dts: r8a7795: salvator-x: Add support for R-Car H3 ES2.0")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Stream of fixes has slowed down, only a few this week:
- Some DT fixes for Allwinner platforms, and addition of a clock to
the R_CCU clock controller that had been missed.
- A couple of small DT fixes for am335x-sl50.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZR3FwAAoJEIwa5zzehBx3MmsQAJ+VV9hfqtXihWZFTqM+RqLO
0qn4BU+zpxS/4TK/cVXy69/PNXRJJqq0hPfmyfBPj3Mm5revejFaFg7w620mBvUy
01w1Wu2bLf6HG+9PBjmwBl9CIG4qjSHQXKvkT3A/ZVvV1zw+V/Yvs48Y7e7CDYMc
or+URw9JS5R8UZdJ03oklnkNdSRLfXCfjfwKz6Hn1WmZ30Gsg74DYBuGzvL2wFRx
qyBaNwTaItipiIIPSzrns4yexpujYwzMxypIF6q9cHXfmnA669NwHCUwhZawdvQi
ibEoGxTpisjus07/y+zcar73f+NFN3QVtKdTi+XxYTKBPH3OxU4d4DbbE4EBpazk
G/I8ZVZ87tpuskkLegTuXDjsgfsVJTdBt+Rck4+MGiP/4DccOXXauEsGhbryk5Jg
TB6r45tf9pDpoYiCF0JIkkl9TLEv4hUXgIYZBYtH1lFXbSVkGpk1y+ZM3SrgSoP1
U2wAY6vxAB6taGHI/99i3/8VI5Fd7Q06XpaGVyk9ET7pRc5Lvpbz9255jpLOasf/
8ZkaVk3yM9mzcSEezHohzQd2en1sIvA6gZbLFMBL9UoLBgrtbSJPQCIalnRelwJf
SZoO/mDmgYAr3Tq3NuYUI4dp1U49q5nGme6ujm98Hg5VdH/50ZDwidaFS/N+Ba71
gIc2TLD0OMC/zhuOOBaE
=pi+d
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Stream of fixes has slowed down, only a few this week:
- Some DT fixes for Allwinner platforms, and addition of a clock to
the R_CCU clock controller that had been missed.
- A couple of small DT fixes for am335x-sl50"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: allwinner: a64: Add PLL_PERIPH0 clock to the R_CCU
ARM: sunxi: h3-h5: Add PLL_PERIPH0 clock to the R_CCU
ARM: dts: am335x-sl50: Fix cannot claim requested pins for spi0
ARM: dts: am335x-sl50: Fix card detect pin for mmc1
arm64: allwinner: h5: Remove syslink to shared DTSI
ARM: sunxi: h3/h5: fix the compatible of R_CCU
- A series from NXP employee Li Yang that updates the copyright claims
to comply with company policy.
- A patch-set from Madalin Bucur that adds Data Path Acceleration
Architecture (DPAA) QBMan and FMan. Quite a few .dtsi files are
created for SoCs with different DPAA configuration to include the
devices as needed.
- Enable UHS-I SD and eMMC support for LS1046A and LS208xA RDB/QDS
boards.
- Enable TMU device for thermal management support on LS1088A.
- Update SATA device node for LS1088A with correct compatible and ECC
register bit.
- A few small random device tree updates.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJZRpzyAAoJEFBXWFqHsHzOiB0H/2j7iQRVuiwINPE1VlIyWIrC
GrBVcf3chm0R/9E87LtX0PdgX2FweKyQ6AHDK2A8zM68pavX70LGVRfKSYqFoVN8
dEIAHhvNiLMVCPbxiuDtYSsWBSnWLM5+PEpy6pUSej9A/9m6KLyeX82+0QYL/tL0
/DaN+vwVQm5GYi/5KiK3JQ765Vva435ImYf3+N15Jra5NXVDn4myInOOcvcX6zK+
WtTckAyJT9e8KLfNA5UT39KbRRD8sZjlIF75TGu6RJGT1KWbU+atzEp1L9Nwgg51
+5pW11vs5ADoqFiT6LdjGjFf1WJEphWbLoDknDr+QJJThi1mCMy2pU7xMVUF86I=
=uI6T
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
The Freescale arm64 device tree updates for 4.13:
- A series from NXP employee Li Yang that updates the copyright claims
to comply with company policy.
- A patch-set from Madalin Bucur that adds Data Path Acceleration
Architecture (DPAA) QBMan and FMan. Quite a few .dtsi files are
created for SoCs with different DPAA configuration to include the
devices as needed.
- Enable UHS-I SD and eMMC support for LS1046A and LS208xA RDB/QDS
boards.
- Enable TMU device for thermal management support on LS1088A.
- Update SATA device node for LS1088A with correct compatible and ECC
register bit.
- A few small random device tree updates.
* tag 'imx-dt64-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (22 commits)
arm64: dts: ls1088a: update sata node
dt-bindings: ahci-fsl-qoriq: add ls1088a chip name to the list
arm64: dts: ls1012a: Add coreclk
arm64: dts: ls1046a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: ls208xa: disable SD UHS-I modes by default on RDB
arm64: dts: ls1043a: Add generic compatible string for I2C EEPROM
arm64: dts: add LS1046A DPAA FMan nodes
arm64: dts: add LS1043A DPAA FMan support
arm64: dts: add DPAA FMan nodes
arm64: dts: add LS1046A DPAA QBMan nodes
arm64: dts: add LS1043A DPAA QBMan nodes
arm64: dts: add DPAA QBMan portals
arm64: dts: ls1088a: Add TMU device tree support
arm64: dts: ls1088a: update the sata node
arm64: dts: Add flash node for ls1088a qds and rdb
arm64: dts: ls1088a: add esdhc node
arm64: dts: ls1012a: add eSDHC nodes
arm64: dts: ls208xa: support SD UHS-I on RDB and eMMC HS200 on QDS
arm64: dts: ls1046a: support SD UHS-I and eMMC HS200 on RDB
mmc: dt: add compatible into eSDHC required properties
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Improve the mcbin support (Armada 8040 based board): add sdhci and
the second 1G port
- Improve crypro nodes description on Aramda 7K/8K
- Use new binding for ap806 clocks
- Improve mdio nodes and add xmdio on Aramda 7K/8K
- Add second SGCI node on Armada 37xx
- Improve the description of the Armada 3720 DB board
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWUTPlSMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71VOLAJoC5+faPv4o
ob78Tena5JEbNcQtlQCeKrl7v3V4DP3BMhlBa9eguRn4RRQ=
=LHta
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.13 (part 1)
- Improve the mcbin support (Armada 8040 based board): add sdhci and
the second 1G port
- Improve crypro nodes description on Aramda 7K/8K
- Use new binding for ap806 clocks
- Improve mdio nodes and add xmdio on Aramda 7K/8K
- Add second SGCI node on Armada 37xx
- Improve the description of the Armada 3720 DB board
* tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add xmdio nodes for 7k/8k
arm64: dts: marvell: add a comment on the cp110 slave node status
arm64: dts: marvell: remove cpm crypto nodes from dts files
arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot
arm64: dts: marvell: Enable second SDHCI controller in Armada 37xx
arm64: dts: marvell: armada-37xx: Use angle bracket for each register set
arm64: dts: marvell: armada-37xx: Align the compatible string
arm64: dts: marvell: armada-3720-db: Add information about the V2 board
arm64: dts: marvell: armada-3720-db: Sort the dts node alphabetically
arm64: dts: marvell: disable the mdio nodes by default
arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB
arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k
arm64: dts: marvell: 8040-mcbin: Enable 1GB Ethernet
arm64: dts: marvell: cp110: add required clocks for mdio interface
arm64: dts: marvell: use new binding for the system controller on ap806
arm64: dts: marvell: remove clock-output-names on ap806
arm64: dts: marvell: add second 1G port on the Armada 8040 DB
arm64: dts: marvell: mcbin: add sdhci
arm64: dts: marvell: add clocks for Armada AP806 XOR engines
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add reset control properties for audio to r9a779[56] SoCs
* Add add DMA for IIC_DVFS to r9a779[56] SoCs
* Add support for Salvator-XS and H3ULCB with R-Car H3 (r8a7795) ES2
* Add missing index to PWM pinctrl subnode name to Salvator-X board
* Add 12288000 for sound ADG to Salvator-X and ULCB boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZQ9NmAAoJENfPZGlqN0++YKQP/29K6aCDPyztpPHBpmDs6oEx
viTr0YTxyIBD256Z+gJMxlDRm36HZzZFRzFdLn2c5iGjHt/jXY5bPTvMR9FkPUDJ
OHB1SPOVoyYdy0l+ti+RdO4JoIM295auueL4vlyVLz0co/3q97RUWlfVclZtuIx7
k4m0hhmFgeVloNFYIOOKWr60MHcz5tw1tEm48wsLk2hg9OkugkbIdEo64rq6Q08G
2Sw87T9+4K2TGA8RV0ypjlZ/xfryfnGbDy2bNQNDyph+5NK6KrJYdoj4vUTzfPLX
1e2uIF9KcTMiAf6BVtx/rTAXM2i3F4xAlL3FNyqLMIfAkIWwVZ62Jf22BFQ4QQ1m
lcE9wsP1zDO7DvaqGsuq3kyA8eZ7w1UHo+Xx7rpin1hl4D7H53jDyXWpDJqyAuYH
/lxTCQ2y3sdsixHINwLD2Dgmv7O5OaHiqMH0rPGcoaayqDWNm1j8SqxMNvU5hUKp
6jMmZST55+P52nYlAJPP4zVcJ6BzBhMa4tcaTth6cg6fAFF68kHyeeahjRgh3PS3
Fqt+mrXey1meWpBsWGJsnpgcDAVcVEDqOI9eDKm7vQFWi6bfn46feYw7geiPiABf
IPDITrmnKJXlP2wjz1Uw3kRSbG9cl36vgVWLdqaq7P37xRgmkL1R5bYo/u/UUW/N
kkWe3GgcxbwtNoCeNkxr
=wed7
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt2-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Second Round of Renesas ARM64 Based SoC DT Updates for v4.13
* Add reset control properties for audio to r9a779[56] SoCs
* Add add DMA for IIC_DVFS to r9a779[56] SoCs
* Add support for Salvator-XS and H3ULCB with R-Car H3 (r8a7795) ES2
* Add missing index to PWM pinctrl subnode name to Salvator-X board
* Add 12288000 for sound ADG to Salvator-X and ULCB boards
* tag 'renesas-arm64-dt2-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7796: Add reset control properties for audio
arm64: dts: r8a7795: Add reset control properties for audio
arm64: dts: renesas: Add support for Salvator-XS with R-Car H3 ES2.0
arm64: dts: renesas: Add common Salvator-XS board support
arm64: dts: renesas: Extract common Salvator-X/XS board support
arm64: dts: salvator-x: Add missing index to PWM pinctrl subnode name
arm64: dts: r8a7795: h3ulcb: Add support for R-Car H3 ES2.0
arm64: dts: r8a7796: add DMA for IIC_DVFS
arm64: dts: r8a7795: add DMA for IIC_DVFS
arm64: dts: ulcb: add 12288000 for sound ADG
arm64: dts: salvator-x: add 12288000 for sound ADG
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the CCPLEX cluster on Tegra186, which is used to initiate CPU
frequency and voltage transitions.
Also included is a bit of cleanup for PCI related device tree content,
in preparation for a future DTC release that has additional checks for
the PCI bus.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAllDkc0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoVAtEACNPwpKvx7jTNmP8Z2nGARRU/7X5PjK
BXRd3C4IgCgOmUHrUQCOvxPVdtYqc/lyW7Bs8v3jo3o5eOG+glXoZ/QRRlwKmBnV
hJrxT4qfgC0MwdXdukbxQ44wP4ehQdZBTxhyBuRHj0JpW6/cJ8DKfe6hNYhexzR0
sUXiRzf6VskehZHVeowkqNNoltoEsIzwshIwWKh1Z6gZydPHTmop3jd+v/iWFBj6
jDkF1FZv80I+MulChz5enGEKq1b5E9E0IU9zd8jnelqRAqCDy+xw7x1sGg6KM2st
z3lL17msDPV73KBWfyPJ20vIodFfY9WUlQ4E3DzHHTkdUUMBzQ7C804c4HPf/8KE
rF9/0Kr+JFOuzo8znHtvz8WQiimK3X8BH7MwhuFNlfzniu3PPqBeFmf/mZcxl1Cx
xf17l43tTM14e7+8rjVMmuIfqCnrIbW0bmr74YgU20VOvdQ1T0VUBQCFDG3bU+zT
t4ljt7G8/i4SoWf1eVUtv7PW/miwEb8qnjx7yfHS7Qzfjhr+z3OxorqIdc1A0n4l
rxVBkpjRpcRyXicmF8j+aT3cU5inVQ0UnvKbkiFmsia3hIPKlAnLJXFQLvTRizKa
1BXa0HH4QvQxnmLzVGx9aOcndI1XoCMmNQMAdFeC4XXD7IDJ8CXke9hVU875cj6V
YWX4IqtXljIDgg==
=nFWX
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
arm64: tegra: Device tree changes for v4.13-rc1
This adds the CCPLEX cluster on Tegra186, which is used to initiate CPU
frequency and voltage transitions.
Also included is a bit of cleanup for PCI related device tree content,
in preparation for a future DTC release that has additional checks for
the PCI bus.
* tag 'tegra-for-4.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: dts: nvidia: fix PCI bus dtc warnings
arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Adds support for Coresight CPU debug MMIO interface on all Juno variants.
2. Enables support for few SMMUs on Juno which were previously disabled
waiting for IOMMU-backed DMA API support to be stabilised.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJZQmvdAAoJEABBurwxfuKYob0P/RB2bYmP0bjlIP/QRII1b3tI
nlBIWQIcOSzedLK3sayK3WCSsyYeLAQP9Y3qRM6GJwzTd5fGHJNUzwEHKhxvml+6
H8z/7ym0OoIRYdY40OyOdao+9uKm1A7i399KPKd+1Ukwfu/1eKyBRMIuqbo/PQ+I
yCDhlEPCWTPpUQF4gAslowg9HYSeUtbfFtekT+BqA9MHz0pp8Btr3yOTUhaHy5w7
MGV4sQfi9IqwBqvy5BDR7byFoGzYdZJN0MEQkQyjK08fJITNRzrUOHffbEWcQ6N8
Q4yCay0BpNw0JMCwEJmsysKw0XyPTyPSVZdfoFH9gTxDEymxSv+GYeoqSEhjpvWM
6SESHyfBGuEbYCITQafeD1bS9vI3bbgpoUj7aw6tql1gW2GusUV7PJACjIIkp24M
LurfA/WgBLn2NUYC5GG5e919EzDFKzHwe4fJA6tfSf14pq/a3HUpFoArn/z9vX2k
UnGmFHpWCoRff3ZaEI9d8faHoHhU4h0hNaTFhPAAT+4YF/Vz4Bj/2wilUTO3AQ98
zX1cEsxQFQjPl1JjpWXeEASgsK9KmnV13eVMgWpUuUzbHZoifzwvuBOSIQA8QXh5
z0Jh7zM26n8SAB6JxI74Imw4b5eXWPZDSPsbUXeGW5VjENzzue3fBaieLO6Q3t4d
YEAJXL+pJTBLQL/dZHQL
=BIsT
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
ARMv8 Vexpress/Juno DT updates for v4.13
1. Adds support for Coresight CPU debug MMIO interface on all Juno variants.
2. Enables support for few SMMUs on Juno which were previously disabled
waiting for IOMMU-backed DMA API support to be stabilised.
* tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: enable some SMMUs
arm64: dts: juno: add coresight CPU debug nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Just like the H3, this is mostly about enabling the EMAC on the H5, and
also has a new board, the Orange Pi Zero Plus 2
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZQZulAAoJEBx+YmzsjxAgdrIP/2Y+cVwgdqbe3JzIy2xAbboe
5/jYgEkrxT9u0yFefKZCbPMUnz9q9hBjqYHnTRwzTMuIGvSqsxgWqsVBL+OZoFHk
s3OUJOm0FnRV+5Er1NMbfkfW2rRmeQzsCYpKMf6bTkfyIAk4rSqMnB5ruZCYINbZ
OyNO7IFQ7ryORGpRT8F70dNeqsN7wxtWAhNN+FWC0UaHAZbXFZqGny5YINGghX1h
74gy8hU4/qQZfHd+IBFf2v/WB1TYgNFHxKMfnoHvj3NQtWtV8GqQg3X32tY4YI7t
S873vCYZhqLLlGJYPbScFjsVCr8pW2851fZxfvd2cUNQR65b7EzJAI25+9N7aPau
rZVDi2eUZlchmEZhpg1W4k5xcBhXjXvaK11dOyue48S9WI1PcAMeI19vRm4AhFqm
p6v5UTUgJpD/pKP7ZkrpXdi5rg4jjQ+JNltjeks9vcakDg+feiOlq8euNq2Vq8Wu
vML1s15CL2WHVD/4FiDTUHKgz6v86+ksYqY0VOnr2eWGLrlkb8XtV7HlCfzFUuJ3
V0v7d45wuW/renvGziTwhxqyA7h+V/R5rww+/HwSGOuAY7KtATYVfpNWIX/aYNEU
aeEVR4FtN+usgKCMBnieD9FfN7Qe86aFq1d5hCaWrgKooZ9TaLlWN6RQuWJ/NTf5
YvA3keSVdqByZBgw1PkT
=x40b
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-h5-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner H5 DT changes for 4.13
Just like the H3, this is mostly about enabling the EMAC on the H5, and
also has a new board, the Orange Pi Zero Plus 2
* tag 'sunxi-dt-h5-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: h5: Add initial Orangepi Zero Plus 2 support
arm64: allwinner: h5: enable dwmac-sun8i for Nano Pi NEO2
arm64: allwinner: h5: enable dwmac-sun8i for Orange Pi Prime
arm64: allwinner: h5: sort the device nodes in / part for some boards
arm64: allwinner: h5: add support for NanoPi NEO2 board
arm64: allwinner: h5: add support for Orange Pi Prime board
arm64: allwinner: orangepi-pc2: Enable dwmac-sun8i
arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module
ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros
Signed-off-by: Olof Johansson <olof@lixom.net>
A few fixes around the PRCM support that got in 4.12 with a wrong
compatible, and a missing clock in the binding.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZQZkZAAoJEBx+YmzsjxAg4nAQAJJqzy8//Ur0o6Ppc6eufIAY
gYGS80x5n/a6/X7PPMj/cMBVc1/HoOoF5YVKry2edRi4jKwpBjCE6THNJ/EdI0LM
6PrN4y9yJAzxbwWfD9rfVNLg54665TGW8etBp5C3Sqdi+qmU9BTL068UYGcA46I8
XGZ53wGLnCfRH5VGpVzxORbdQMStKsZ2D0PTmZ7aJU2nrPugbf4DiGg2Uhgdx+bI
Mz3Zl6cZQraWdl6gSVTjG1Z5LQOKo5tXGIaC4zxbXe/Ss2lspxM3WKtJDhdtoTH9
ZiLGDf6Q3XUeMN5WkQNT6ZnT8+/8NQujhcktEfxhfiA5pGeHLzuOCaOLgEWVy8sc
Z6jNLHUht3W/XGOGY0szKfqmsOnDdnsnv3YbCUoWJ/0ER8kwQdJ8k4iI1EVMi23Q
UcXDiZivCgjj7mYOzfhG2YYZ03rxhadPqsnoDro/a+mI6splPhQplJC/we8TUYHt
eJmXF3rvOgXGYJAdnF8FJiftzUKUd0h8S8qsxBB3knP4mPY73vtppsvJwPOqlil2
EPcqHmcd3EvHRZrmHNsP7qpQXMiaWqImf6Ioq7hz4mPPJ5uiIPrEIdRmACCAdn9H
eeOQyI0rdg3bTCKi/dztaX4zVCMjEy9HG0xZ/Y6dvPwKjuWTpJApsTC+xEaiql2L
gQ+OFMX4mvgr79OUNp7L
=WD1J
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Allwinner fixes for 4.12
A few fixes around the PRCM support that got in 4.12 with a wrong
compatible, and a missing clock in the binding.
* tag 'sunxi-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: Add PLL_PERIPH0 clock to the R_CCU
ARM: sunxi: h3-h5: Add PLL_PERIPH0 clock to the R_CCU
arm64: allwinner: h5: Remove syslink to shared DTSI
ARM: sunxi: h3/h5: fix the compatible of R_CCU
Signed-off-by: Olof Johansson <olof@lixom.net>
Our usual arm64 changes. The most notable things are the EMAC support and
USB support enhancements. There's also support for the SoPine SoM, and the
OrangePi Win.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZQZR6AAoJEBx+YmzsjxAgbdsP/Ajq3CXNiJE9iMHdcQhDt/JA
4nUQuzP4F00HTd4C8xwl/17zNic1X/irSKg7bdm9vCYmW5wD1TT9OwsLaJZLCbgk
63+MHuxObvVmjpIoVs9rjT40H1v4b3bGPJmHhBL/RIvkO9yKAfqQ9Yw1Wk5XXfNf
N6d06GgnpYyVYVuL2IJqTYeJqqk6uh+9gi4FjEVZmpL6zdPzLe9P4AVrHgsj3QK1
Y6xZzo3YY4ulHE99LQkLpT4RJP4Fqpalb8vE3+xmn/OcSA2O+wwNvrYxatW9mp9O
Qs0FEem4o3x50Oz5DVnml/BbsnDeI5nzGIm+gwHQxYOq1Jrab7N0og61Lb8oXos2
fxYqF7tHLKvCXjY7df+tLpkGjqPuF11KoM7xKM65bF7PfvXAmUq+tj/6ZWdLFIqk
JEYhP/xoRIli+m8blH/AmH7XZBQ7+HRJOHHmwsshozR4u4ty3WRSJDOG3SvGWKPh
txDHynuHN8ahevohRPMDYLutaAX8U2recj47Rm33Q89sFsHIbJ4OtkHIQGzgld0M
aj8K7fnRayWUp9J5jDjhLaQazP3F3aeCazdTA8+KqERhvJUodNYZM1Wps3PVipxg
9O/iQbCXivJaqFjRfgnoenh84G0pRzpXt8mM2fYyam7W1bzhEzJTl4+G08N2DxSg
KrhqR1bXR03D5qnX8y3N
=MCTy
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner arm64 DT changes for 4.13
Our usual arm64 changes. The most notable things are the EMAC support and
USB support enhancements. There's also support for the SoPine SoM, and the
OrangePi Win.
* tag 'sunxi-dt64-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: Add initial Orangepi Win/WinPlus support
arm64: allwinner: a64: add device tree for SoPine with baseboard
arm64: allwinner: bananapi-m64: Enable dwmac-sun8i
arm64: allwinner: pine64-plus: Enable dwmac-sun8i
arm64: allwinner: pine64: Enable dwmac-sun8i
arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
arm64: allwinner: sun50i-a64: Add dt node for the syscon control module
arm64: allwinner: a64: add DTSI file for SoPine SoM
arm64: allwinner: a64: Convert CCU raw number references to macros
arm64: dts: allwinner: pine64: Prepare optional UART nodes with pinctrl
arm64: allwinner: a64: enable RSB on A64
arm64: dts: allwinner: pine64: Add remaining UART aliases
arm64: dts: allwinner: a64: Add UART2 pin nodes
arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
4.13. Please note the following from Eric:
I've based this summary on the bcm2835-dt-next tag, to clarify what's in this
patch series, but it does require being careful since it involves a cross-merge
between branches.
- Anup documents the Broadcom Stingray binding, common clocks, adds initial
support for the Stingray DTSI and DTS files and adds support for the PL022,
PL330 and SP805
- Sandeep adds the clock nodes to the Stingray Device Tree nodes
- Pramod adds support for the NAND, pinctrl, GPIO to the Stingray Device Tree nodes
- Oza adds I2C Device Tree nodes to the Stingray DTSes
- Srinath adds PWM and SDHCI Device Tree nodes for the Stingray SoC
- Ravijeta adds support for the USB Dual Role PHY on Northstar 2
- Gerd starts adding references to the sdhost and sdhci controllers, and then
switches the sdcard to to use the SDHOST (faster than SDHCI)
- Stefan defines the BCM2837 thermal coefficients in order for the Raspberry Pi
thermal driver to work correctly
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJZQEIyAAoJEIfQlpxEBwcEtZoP/jSCkP5BsHM9i5PWCjZ8TTTb
359QZNjT2TDE08nqrdIOoeu2LUBFcqlVBR/IROyMJEkyY7AmGJ/S/s8OGI7DI5kw
3KaJYPl3YQ3VKfFK3MrsSwSDHUB9yvHzFd2sOrxWNT42N+mYykq61oqPAxHnVbMU
zd9e1SiJL6iWYlEjE0vvqYv5I8V6I9r8fZV35qBmEZLO0PkJBklWOiubs1Z4j0IM
cZjbG/MGsjdAyUoIHxxkx1QK8/4ivKvnNxa28wLD+1Trj5CvwcL0sMdBP/pPCZD2
QM5DjBpq5O5LNCOPA1YDOCCgKus9JkNBPTlSHlg6HeBl7WEjefQqhQd3pVnsQhzL
U/1DeUc4taPPssCvtE2RJPXz8JB1U6iNY85z1wwT5oqKJW0JwzB04yHVLcRz8oUJ
yb719jXnvWEJb56E+LjvnRsoICwSX4clNQyWvKsRcwmwZ82PFsZzCiqGZsmXydrs
/m9wyGlPKvkJgFdN9rwcuIMWI4KMLIO7mmPqY9kHahRjNCp9gm+4KS/oEli0/2So
he7zKa/45JlAmaFX2bK2oPiUPhI1puXEW2GTfl+5zDe9ZstZX7N7DIc1DCs2ebYB
MrqBgYTZYB1GRhiny0cgRJhTBcdtqpKIt/RjJVDnXTAwI8N8icnwp3rNmYv6OgxR
IY6trZH7vw2BSp4lIJ1j
=QtXg
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
This pull request contains Broadcom ARM64-based SoCs Device Tree changes for
4.13. Please note the following from Eric:
I've based this summary on the bcm2835-dt-next tag, to clarify what's in this
patch series, but it does require being careful since it involves a cross-merge
between branches.
- Anup documents the Broadcom Stingray binding, common clocks, adds initial
support for the Stingray DTSI and DTS files and adds support for the PL022,
PL330 and SP805
- Sandeep adds the clock nodes to the Stingray Device Tree nodes
- Pramod adds support for the NAND, pinctrl, GPIO to the Stingray Device Tree nodes
- Oza adds I2C Device Tree nodes to the Stingray DTSes
- Srinath adds PWM and SDHCI Device Tree nodes for the Stingray SoC
- Ravijeta adds support for the USB Dual Role PHY on Northstar 2
- Gerd starts adding references to the sdhost and sdhci controllers, and then
switches the sdcard to to use the SDHOST (faster than SDHCI)
- Stefan defines the BCM2837 thermal coefficients in order for the Raspberry Pi
thermal driver to work correctly
* tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: Add USB DRD PHY device tree node
ARM64: dts: bcm2837: Define CPU thermal coefficients
arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
arm64: dts: Add I2C DT nodes for Stingray SoC
arm64: dts: Add GPIO DT nodes for Stingray SOC
arm64: dts: Add pinctrl DT nodes for Stingray SOC
arm64: dts: Add NAND DT nodes for Stingray SOC
arm64: dts: Add clock DT nodes for Stingray SOC
arm64: dts: Initial DTS files for Broadcom Stingray SOC
dt-bindings: clk: Extend binding doc for Stingray SOC
dt-bindings: bcm: Add Broadcom Stingray bindings document
ARM: dts: bcm283x: switch from &sdhci to &sdhost
arm64: dts: bcm2837: add &sdhci and &sdhost
ARM: dts: bcm283x: Add CPU thermal zone with 1 trip point
ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v6)
Signed-off-by: Olof Johansson <olof@lixom.net>
mt8173:
- split USB SuperSpeed port in HighSpeed and SuperSpeed ports.
- move USB phy clocks up in hierarchy to met new bindings description
- move MDP nodes up in hierarchy to met new bindings description
mt6797:
- add basic SoC support
- add clock driver
- add power domain
dt-bindings:
- clean-up i2c binding description
- add binding for mt2701 i2c node
- add fallback compatible to scpsys binding description
- add bindings description for mt7622 and mt6796
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJZPmpvAAoJELQ5Ylss8dND8NwQAI4LIEM7orrUJDBwnrXWRhXC
O5UzuKG6S+cUqY4l/8z2pEcEjMxqcVY2NqtbUToJKc6ZXw08ho/VfMMUKjiAFj0C
Xhtmis7G5srIIxd9cNuajPQ9zkUAkFNFJzQOirJTfZibyPbHcXuJW94/8qGztXKj
QDsxWg4aPL35KPXZlhVAqya1hIXRlT49OaIH1qhCO0ZOpIWWH6Rj9c1lCmZA4B9o
o9SmTg0PktG3r0LGT+2A9PQ0eukKKqGMSku+dUq5Uw/YxvHNO+qdyw0ZxUYyOrw2
aM/WKZeEPamfgVl5a6G+0iCxZbZqnwlIgjuHvKp87jNgEx+apUoBuweoSi+N4J/W
a4efrgATcgseiMb8NNgj6AmvZr67rocG1ZOnMXazOUPj6hixMb2i3Zm7vm1wCezr
gYV+dTUQwhyEIcJU3joju2xt4Ll7yWJlGvixeu8eFg5N/R6m12D49+tCgc93GA7v
NXWDrX9/MdU9GwmuqvrAQAh/0DlmQkU32DxmQxqvPF+A0OzEzeYankLGlEe45wef
CAsZMSO8DKmPfrKvEUR99aEthNkrzbg6Iiyl5EUWf1qNsXqXmaou2h+hoQaMsi4/
qCjQFO8F7bztJqCQAr+Ym95bFv2dpb2B+2S+7eb24V6OifxtWLwYDQywEJPekZft
7oOp24vJYzWl/dabwjmC
=H12B
-----END PGP SIGNATURE-----
Merge tag 'v4.12-next-dts64' of https://github.com/mbgg/linux-mediatek into next/dt64
Add device tree nodes for
mt8173:
- split USB SuperSpeed port in HighSpeed and SuperSpeed ports.
- move USB phy clocks up in hierarchy to met new bindings description
- move MDP nodes up in hierarchy to met new bindings description
mt6797:
- add basic SoC support
- add clock driver
- add power domain
dt-bindings:
- clean-up i2c binding description
- add binding for mt2701 i2c node
- add fallback compatible to scpsys binding description
- add bindings description for mt7622 and mt6796
* tag 'v4.12-next-dts64' of https://github.com/mbgg/linux-mediatek:
dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC
arm64: dts: mt8173: Fix mdp device tree
dt-bindings: i2c: Add Mediatek MT2701 i2c binding
dt-bindings: i2c-mtk: Add mt7623 binding
dt-bindings: i2c-mtk: Delete bindings
dt-bindings: i2c-mt6577: Rename file to reflect bindings
dt-bindings: mtk-sysirq: Correct bindings for supported SoCs
arm64: dts: mediatek: add clk and scp nodes for MT6797
dt-bindings: mediatek: add MT6797 power dt-bindings
arm64: dts: mediatek: add mt6797 support
dt-bindings: mediatek: Add bindings for mediatek MT6797 Platform
arm64: dts: mt8173: move clock from phy node into port nodes
arm64: dts: mt8173: split usb SuperSpeed port into two ports
Signed-off-by: Olof Johansson <olof@lixom.net>
make usage of pci switches possible; some more qos and pinctrl nodes on
rk3399; updates for the rk3399 cpu operating points including separate
opps for the higher rates OP1 variant of the chip and mmc-nodes for
the rk3328.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlk5yQ4QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgU7rCACdo8/RlAH58lR+35ZkJ3hAFHAlJJ9l2GFW
pobp2PYjtSCLaHz2o9yU7tT0peNph3YoeL9rFS44U/NUwtE4eloPbPea/FaGJ0nW
LUP6Y5bnM8sJMmO3YrG6Y3ryjTFD9GGe9IzSDgQhai+rXPfo/FZ+a1krpNN3HrJN
dd6PIozaa5aJpDkpET7NyvTRePMiDmuJAoj/9atDr8MLDKuuKNqQtnKcXGJ+3gUb
Zc4Ltxy2uTtc9bFi05Bi19AnZIqDXAGQdU+u+lqUGps3f8Q63iWYU/OEiCw3Oozs
3RJ7KXSZ58JN1CXwxMUE1OFplF5fVvPsv4Vzg8ddJ+vOK4E4t8Pd
=UMmB
-----END PGP SIGNATURE-----
Merge tag 'v4.13-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Support for the new rk3399 firefly board; extending the pcie ranges to
make usage of pci switches possible; some more qos and pinctrl nodes on
rk3399; updates for the rk3399 cpu operating points including separate
opps for the higher rates OP1 variant of the chip and mmc-nodes for
the rk3328.
* tag 'v4.13-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: update common rk3399 operating points
arm64: dts: rockchip: introduce rk3399-op1 operating points
arm64: dts: rockchip: enable usb3 controllers on rk3399-firefly
arm64: dts: rockchip: add ethernet0 alias on rk3399
arm64: dts: rockchip: bring rk3399-firefly power-tree in line
arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs
arm64: dts: rockchip: extent IORESOURCE_MEM_64 of PCIe for rk3399
arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399
arm64: dts: rockchip: add pinctrl settings for some rk3399 peripherals
arm64: dts: rockchip: add some missing qos nodes on rk3399
arm64: dts: rockchip: add support for firefly-rk3399 board
dt-bindings: add firefly-rk3399 board support
Signed-off-by: Olof Johansson <olof@lixom.net>
Add Device Trees for Actions Semiconductor S900 SoC and
uCRobotics Bubblegum-96 board.
UART0/1/4/6 interrupts are guesses.
Cc: 96boards@ucrobotics.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
Add the description of the xMDIO bus for the Marvell Armada 7k and
Marvell Armada 8k; for both CP110 slave and master. This bus is found
on Marvell Ethernet controllers and provides an interface with the
xMDIO bus.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The cryptographic engine found on the cp110 slave is disabled by default
because of some known limitations. Add a comment to explain why it is
disabled by default.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The cryptographic engine on the master cp110 is now enabled by default
at the SoC level. Remove its dts nodes that were only enabling it.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Enable the cryptographic engine at the SoC level on the master cp110.
This engine is always present and do not depends on any pinmux
configuration.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
By adding this regulator, the SD cards are usable at higher speed
protocols such as SDR104.
This patch was tested with an SD HC card compatible with UHS-I.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second
one.
Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces.
The second interface is using pluggable module that can either
have an SD connector or eMMC on it.
This patch adds support for SD module in the device DT.
[ gregory.clement@free-electrons.com:
- Add more detail in commit log
- Sort the dt node in address order
- Document the SD slot in the dts ]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
When several groups of register address and size are used with reg, then
surround each one by angle bracket.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The initial device tree file was for the board V1.4. Now the V2.0 board
is also available. The same dtb will work for both, but the CON number
have changed, so update the comment in the dts to reflect this.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Sort the reference nodes in alphabetical order to ease the merge of
future nodes.
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Disable the mdio nodes by default in the cp110 slave and master dtsi as
they're not wired on every board.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell
Armada 8k DB. This is needed as the MDIO nodes will be disabled in the
CP 110 slave and master dtsi by a following up patch.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The EIP197 cryptographic engine supports 64 bits address width but is
limited to 40 bits on 7k/8k. Add a dma-mask property in the
cryptographic engine nodes to reflect this.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Enable the 1GB Ethernet interface that lives on the slave CP110,
with its corresponding phy (that oddly lives on the master CP110).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the three required clocks for the MDIO interface to be functional
on Armada 8k platforms. Without this, the CPU hangs, causing RCU
stalls or the system to become unresponsive.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[Thomas:
- remove mg_core_clock, since it's a parent of mg_clock
- also add clock references to the slave CP mdio instance]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
