Commit graph

4 commits

Author SHA1 Message Date
Stephen Boyd
5d806f9fc8 clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
This kzalloc() could fail. Let's bail out with -ENOMEM here
instead of NULL dereferencing. That silences static checkers. We
should also cleanup on the error path even though this function
returning an error probably means the system won't boot.

Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06 14:48:32 -08:00
Chen-Yu Tsai
3de64bf187 clk: sunxi-ng: Support separately grouped PLL lock status register
On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.

Add a flag to support this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:36:20 +01:00
Chen-Yu Tsai
ed0ab11023 clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
The condition passed to read*_poll_timeout() is the break condition,
i.e. wait for this condition to happen and return success.

The original code assumed the opposite, resulting in a warning when
the PLL clock rate was changed but never lost it's lock as far as
the readout indicated. This was verified by checking the read out
register value.

Fixes: 1d80c14248 ("clk: sunxi-ng: Add common infrastructure")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-10 15:07:01 -07:00
Maxime Ripard
1d80c14248 clk: sunxi-ng: Add common infrastructure
Start our new clock infrastructure by adding the registration code, common
structure and common code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
2016-07-08 18:04:32 -07:00