Commit graph

16 commits

Author SHA1 Message Date
Geert Uytterhoeven
5e776d7b20 ata: Drop commas after OF match table sentinels
It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Add comments to clarify the purpose of the empty elements.
Rewrap entries to a single line to have a consistent style.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> [ahci_brcm]
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-03-07 11:49:10 +09:00
Damien Le Moal
0561e514c9 ata: fix read_id() ata port operation interface
Drivers that need to tweak a device IDENTIFY data implement the
read_id() port operation. The IDENTIFY data buffer is passed as an
argument to the read_id() operation for drivers to use. However, when
this operation is called, the IDENTIFY data is not yet converted to CPU
endian and contains le16 words.

Change the interface of the read_id operation to pass a __le16 * pointer
to the IDENTIFY data buffer to clarify the buffer endianness. Fix the
pata_netcell, pata_it821x, ahci_xgene, ahci_ceva and ahci_brcm drivers
implementation of this operation and modify the code to corretly deal
with identify data words manipulation to avoid sparse warnings such as:

drivers/ata/ahci_xgene.c:262:33: warning: invalid assignment: &=
drivers/ata/ahci_xgene.c:262:33:    left side has type unsigned short
drivers/ata/ahci_xgene.c:262:33:    right side has type restricted __le16

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
2022-01-14 15:17:16 +09:00
Damien Le Moal
815b6cb37e ata: ahci_ceva: Fix id array access in ceva_ahci_read_id()
ATA IDENTIFY command returns an array of le16 words. Accessing it as a
u16 array triggers the following sparse warning:

drivers/ata/ahci_ceva.c:107:33: warning: invalid assignment: &=
drivers/ata/ahci_ceva.c:107:33:    left side has type unsigned short
drivers/ata/ahci_ceva.c:107:33:    right side has type restricted __le16

Use a local variable to explicitly cast the id array to __le16 to avoid
this warning.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2021-12-06 10:07:47 +09:00
Piyush Mehta
fa4b42b2a9 ata: ahci: ceva: Updated code by using dev_err_probe()
Updated code with already prepared dev_err_probe(). It reduces code size
and simplifies EPROBE_DEFER handling.

Also, unify message format for similar error cases.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210305091029.23378-1-piyush.mehta@xilinx.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-04-06 09:25:01 -06:00
Piyush Mehta
9a9d3abe24 ata: ahci: ceva: Update the driver to support xilinx GT phy
SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can be used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for the SATA controller, the below sequence is expected.

1. Assert the SATA controller reset.
2. Configure the xilinx GT phy lane for SATA controller (phy_init).
3. De-assert the SATA controller reset.
4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).

The ahci_platform_enable_resources() by default does the phy_init()
and phy_power_on() but the default sequence doesn't work with Xilinx
platforms. Because of this reason, updated the driver to support the
new sequence.

Added cevapriv->rst check, for backward compatibility with the older
sequence. If the reset controller is not available, then the SATA
controller will configure with the older sequences.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-03-12 07:28:29 -07:00
Thomas Gleixner
9952f6918d treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:52 -07:00
Kunihiko Hayashi
16af2d6584 ata: add an extra argument to ahci_platform_get_resources()
Add an extra argument to ahci_platform_get_resources(), that is
for the bitmap representing the resource to get in this function.

Currently there is no resources to be defined, so all the callers set
'0' to the argument.

Suggested-by: Hans de Goede <hdegoede@redhat.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2018-08-22 08:08:27 -07:00
Anurag Kumar Vulisha
f0a559aae5 ata: ceva: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below

	SATA SMMU ID =  <TBU number>, 0011, 00, 00, AXI ID[1:0]
	Note: SATA in  ZynqMp uses TBU1 so TBU number = 0x1, so
	      SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]

Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values

 Read ID/ Write ID for Non-Data Port0 transfers = 0
 Read ID/ Write ID for Data Port0 transfers = 1
 Read ID/ Write ID for Non-Data Port1 transfers = 2
 Read ID/ Write ID for Data Port1 transfers = 3

Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:27 -07:00
Anurag Kumar Vulisha
26bf3b6658 ata: ceva: Correct the suspend and resume logic for SATA
The present suspend code disables the port interrupts
and stops the HBA. On resume it enables the interrupts and HBA.
This works fine until the FPD power domain is not off.
If FPD is off then the ceva vendor specific configurations like
OOB, AXI settings are lost, they need to be re-programmed and
also since SERDES is also in FPD , SATA lane phy init needs to
be called again (which is not happening in the present sequence)
Because of this incorrect sequence SATA fails to work on resume.

This patch corrects the code to make Suspend & Resume work in normal
and FPD off cases.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:27 -07:00
Anurag Kumar Vulisha
6e037fb770 ata: ceva: Correct the AXI bus configuration for SATA ports
Previously PAXIC register was programmed before configuring PCFG
register. PCFG should be programmed with the address of the port
for which PAXIC should be configured for.
This was not happening before, so only one port PAXIC was written
correctly and the other port was having wrong value.
This patch moves the PXAIC register write after configuring PCFG,
doing so will correct the axi bus settings for sata port0 & port1.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:27 -07:00
Anurag Kumar Vulisha
3bc867de85 ata: ceva: Add CCI support for SATA if CCI is enabled
This patch adds support for CCI in SATA controller if CCI is
enabled in design. This patch will add CCI settings for SATA
if "dma-coherent" dts property is added.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:26 -07:00
Anurag Kumar Vulisha
05e890d843 ata: ceva: Make RxWaterMark value as module parameter
This patch updates the driver to make Rx Fifo water mark value
as a module parameter.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:26 -07:00
Anurag Kumar Vulisha
ff0d63778c ata: ceva: Disable Device Sleep capability
Since CEVA controller does not support Device Sleep capability,
we need to clear that feature by clearing the DEVSLP bit in word78
of IDENTIFY DEVICE data. This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:26 -07:00
Anurag Kumar Vulisha
e8fc8b858c ata: ceva: Add gen 3 mode support in driver
This patch sets gen 3 mode as default mode in ahci_ceva driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:26 -07:00
Anurag Kumar Vulisha
fe8365bbf8 ata: ceva: Move sata port phy oob settings to device-tree
In SATA Speed negotiation happens with  OOB(Out of Band) signals. These OOB
signal timing values are configured through vendor specific registers in the
SATA controller. These OOB timings depends on the generator and detector clock
frequency, which varies from board to board (ex: ep108 and zc1751 has different
clock frequencies).
To avoid maintaing these OOB settings in the driver, it is better to move these
settings to the device-tree node and read from the device-tree.

This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-23 07:09:26 -07:00
Suneel Garapati
a73ed35052 drivers: ata: add support for Ceva sata host controller
Adds support for Ceva sata host controller on Xilinx
Zynq UltraScale+ MPSoC.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2015-06-10 11:15:17 +09:00