Commit graph

14 commits

Author SHA1 Message Date
Lukas Wunner
5e2400f11d
arm64: dts: Fix TPM schema violations
Since commit 26c9d152eb ("dt-bindings: tpm: Consolidate TCG TIS
bindings"), several issues are reported by "make dtbs_check" for arm64
devicetrees:

The compatible property needs to contain the chip's name in addition to
the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0"
rather than "cr50@0":

  tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short
        from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#

  cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$'
        from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml#

Fix these schema violations.

phyGATE-Tauri uses an Infineon SLB9670:
https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/

Gateworks Venice uses an Atmel ATTPM20P:
https://trac.gateworks.com/wiki/tpm

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-01-25 18:10:07 +01:00
Fabio Estevam
e3873abfe0 arm64: dts: imx8mm-venice-gw7: Adjust PCI Ethernet nodes
As per Rob Herring's feedback:

"The ethernet device should have a node name of
'ethernet'. The 'pcie' node name and 'device_type = "pci"' is for PCI
buses/bridges only."

Do it as suggested.

Fixes: d61c5068729a ("arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes")
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-06 11:11:37 +08:00
Fabio Estevam
31e2689b99 arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes
Several schema warnings are seen when running:

make dtbs_check DT_SCHEMA_FILES=pci-bus.yaml

Fix them.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-06 09:53:52 +08:00
Tim Harvey
2854d8cd03 arm64: dts: imx8mm-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-11-27 10:42:05 +08:00
Fabio Estevam
7b2a19c804 arm64: dts: imx8mm/p-venice: Remove lis2de12 interrupt-names
According to st,st-sensors.yaml, the 'interrupt-names' property is
not a valid one.

Remove it to fix the following schema warnings:

imx8mp-venice-gw73xx-2x.dtb: accelerometer@19: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/iio/st,st-sensors.yaml#

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-09-25 09:47:19 +08:00
Marek Vasut
3c033fb139 arm64: dts: imx8mm: Deduplicate PCIe clock-names property
Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-26 16:37:57 +08:00
Linus Torvalds
ae86218328 ARM: DT changes for 5.19, part 1
There are 40 branches this time, adding a lot of new hardware
 support, and cleanups. Krzysztof Kozlowski continues his treewide
 cleanups.
 
 There are a number of new SoCs, all of them as part of existing
 families, and typically added along with a reference board:
 
  - Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L
    general-purpose MPU.
 
  - Renesas RZ/V2M (R9A09G011) is a smart camera SoC
 
  - Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
    cores and deep learning accerlation.
 
  - Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
    and dual Wifi-6.
 
  - Corstone1000 is a generic platform from Arm that is used for designing
    custom SoCs, the support for now is for the Fixed Virtual Platform
    emulation for it.
 
  - Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used
    in upcoming Chromebooks.
 
  - NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
    MMU-less SoC to be added in a while
 
 New machines based on already supported SoCs this time are mainly
 for 32-bit platforms and include:
 
  - Two wireless routers based on Broadcom bcm4708
 
  - 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
    for the industrial embedded market, and on NXP LS1021A based
    IOT board.
 
  - Two ethernet switches based on Microchip LAN966
 
  - Eight Qualcomm Snapdragon based machines, including a smartwatch,
    a Chromebook board and some phones
 
  - Another phone based on the old ST-Ericsson Ux500 platform
 
  - Seven STM32MP1 based boards
 
  - Four single-board computers based on Rockchip RK3566/RK3568
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOp8cACgkQmmx57+YA
 GNk33hAAn/mY+QDyj8sUwtY4AAVtut2QgyBm7NBWLgiYDQx52yBwP7rUxeKyDqZF
 q6LK5z3NA7NN5REpfn6WKBEFo6wkzTzg4Gev/h+9hwLyozch8vl4etBfZGak4A7m
 cLCONZdw4FMCQ10oLq+ib/WJeJv2W700307OkJ3dN73qdbWLRF1hoyG+uMTHuEqL
 If755IR+EYhxYz8CfJhCYb2BcqhRq047n3sEqolZpFtz5oHUW2dADASgWpV+3yNc
 ql8cH0f5OTKbFS1lM4k7cWbMW2vHWx7jZnXZDyMfy3EE5SOb4V/s9JFJSS1pAfPQ
 OWuq194LT+SIXTTT3DQ+lSNcMhlkyeXQ0JQE1wAAp0vov4V8vHGvEGk0MCku5QHp
 zKKONPfcn9aoWtsh4GaCvt0cP0m7lKyjxJvNSjBy2C9dVW8t4UlIVZr+V8hR2Ufp
 SpCCzMbttrcUK6rHzQmWsR563mhfszzuzDfZi4RK2aFLJKhFi5hEQF2tDxLq8Y09
 vIY/OkRpSwahgbiyj/zhKrJtnhFHh1m6wZJG+Sk9lTJikEhaRinriy0lgu08xssG
 krBHPOVhNY11rqlzosBU39JOya1/J2iTxjo7ccNmGfO4MDanE+Cl41a5wSNjciw1
 ihi2zAUBClGg0TnQ+HJylFPS3ZFyGEtbYH/d6td25DtwaaIsaxU=
 =LsM7
 -----END PGP SIGNATURE-----

Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM DT updates from Arnd Bergmann:
 "There are 40 branches this time, adding a lot of new hardware support,
  and cleanups. Krzysztof Kozlowski continues his treewide cleanups.

  There are a number of new SoCs, all of them as part of existing
  families, and typically added along with a reference board:

   - Renesas RZ/G2UL (R9A07G043) is the single-core version of the
     RZ/G2L general-purpose MPU.

   - Renesas RZ/V2M (R9A09G011) is a smart camera SoC

   - Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
     cores and deep learning accerlation.

   - Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
     and dual Wifi-6.

   - Corstone1000 is a generic platform from Arm that is used for
     designing custom SoCs, the support for now is for the Fixed Virtual
     Platform emulation for it.

   - Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in
     upcoming Chromebooks.

   - NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
     MMU-less SoC to be added in a while

  New machines based on already supported SoCs this time are mainly for
  32-bit platforms and include:

   - Two wireless routers based on Broadcom bcm4708

   - 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
     for the industrial embedded market, and on NXP LS1021A based IOT
     board.

   - Two ethernet switches based on Microchip LAN966

   - Eight Qualcomm Snapdragon based machines, including a smartwatch, a
     Chromebook board and some phones

   - Another phone based on the old ST-Ericsson Ux500 platform

   - Seven STM32MP1 based boards

   - Four single-board computers based on Rockchip RK3566/RK3568"

* tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits)
  ARM: dts: kswitch-d10: enable networking
  ARM: dts: lan966x: add switch node
  ARM: dts: lan966x: add serdes node
  ARM: dts: lan966x: add reset switch reset node
  ARM: dts: lan966x: add MIIM nodes
  ARM: dts: lan966x: add hwmon node
  ARM: dts: lan966x: add basic Kontron KSwitch D10 support
  ARM: dts: lan966x: add flexcom I2C nodes
  ARM: dts: lan966x: add flexcom SPI nodes
  ARM: dts: lan966x: add all flexcom usart nodes
  ARM: dts: lan966x: add missing uart DMA channel
  ARM: dts: lan966x: add sgpio node
  ARM: dts: lan966x: swap dma channels for crypto node
  ARM: dts: lan966x: rename pinctrl nodes
  ARM: dts: at91: sama7g5: remove interrupt-parent from gic node
  ARM: dts: at91: use generic node name for dataflash
  ARM: dts: turris-omnia: Add atsha204a node
  arm64: dts: mt8192: Follow binding order for SCP registers
  arm64: dts: mediatek: add mtk-snfi for mt7622
  arm64: dts: mediatek: mt8195-demo: enable uart1
  ...
2022-05-26 10:28:12 -07:00
Tim Harvey
450cec4f7d arm64: dts: imx8m*venice: add missing clock-names to pcie_phy
Define the missing clock-names property for the pcie_phy required by
the fsl,imx8-pcie-phy dt bindings.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05 15:40:21 +08:00
Tim Harvey
4c79865f3e ARM: dts: imx8mm-venice-gw{71xx,72xx,73xx}: fix OTG controller OC mode
The GW71xx, GW72xx and GW73xx boards have USB1 routed to a USB OTG
connectors and USB2 routed to a USB hub.

The OTG connector has a over-currently protection with an active-low
pin and the USB1 to HUB connection has no over-current protection (as
the HUB itself implements this for its downstream ports).

Add proper dt nodes to specify the over-current pin polarity for USB1
and disable over-current protection for USB2.

Fixes: 6f30b27c5e ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc: stable@vger.kernel.org
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-11 09:13:33 +08:00
Johan Hovold
dc90043133 arm64: dts: imx8mm-venice: fix spi2 pin configuration
Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not
muxed for SPI mode and causes reads from a slave-device connected to the
SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and
gw73xx families of boards that got this wrong.

Fixes: 6f30b27c5e ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc: stable@vger.kernel.org      # 5.12
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-06 21:30:55 +08:00
Tim Harvey
9d46d9f782 arm64: dts: imx8m{m,n}_venice*: add gpio-line-names
Add gpio-line-names for the various GPIO's used on Gateworks Venice
boards. Note that these GPIO's are typically 'configured' in Boot
Firmware via gpio-hog therefore we only configure line names to keep the
boot firmware configuration from changing on kernel init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11 11:21:08 +08:00
Tim Harvey
afb424b99e arm64: dts: imx8mm-venice*: add PCIe support
Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11 11:16:17 +08:00
Fabio Estevam
c6fe862aa3 arm64: dts: imx8mm-venice: Fix the SPI chipselect polarity
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:

[    4.854337] m25p80@0 enforce active low on chipselect handle

Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.

The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:

* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.

To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-09-22 10:48:56 +08:00
Tim Harvey
6f30b27c5e arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits
The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development
kits consisting of a GW700x SoM and a Baseboard. Future SoM's such
as the GW701x will create additional combinations.

The GW700x SoM contains:
 - i.MX 8M Mini SoC
 - LPDDR4 DRAM
 - eMMC FLASH
 - Gateworks System Controller (eeprom/pushbutton/reset/voltage-monitor)
 - GbE PHY connected to the i.MX 8M Mini FEC
 - Power Management IC

The GW71xx Baseboard contains:
 - 1x MiniPCIe Socket with USB2.0, PCIe, and SIM
 - 1x RJ45 GbE (i.MX 8M Mini FEC)
 - I/O connector with 1x-SPI/1x-I2C/1x-UART/4x-GPIO signals
 - PCIe Clock generator
 - GPS and accelerometer
 - 1x USB 2.0 Front Panel connector
 - wide range power supply

The GW72xx Baseboard contains:
 - 2x MiniPCIe Socket with USB2.0, PCIe, and SIM
 - 2x RJ45 GbE (i.MX 8M Mini FEC and LAN743x)
 - 1x MicroSD connector
 - 1x USB 2.0 Front Panel connector
 - 1x SPI connector
 - 1x Serial connector supporting 2x-UART or 1x-UART configured as 1 of:
   RS232 w/ flow-control, RS485, RS422
 - PCIe Clock generator
 - GPS and accelerometer
 - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S)
 - I/O connector with 2x-ADC,2x-GPIO,1x-UART,1x-I2C
 - wide range power supply

The GW73xx Baseboard contains:
 - 3x MiniPCIe Socket with USB2.0, PCIe, and SIM
 - 2x RJ45 GbE (i.MX 8M Mini FEC and LAN743x)
 - 1x MicroSD connector
 - 1x USB 2.0 Front Panel connector
 - 1x SPI connector
 - 1x Serial connector supporting 2x-UART or 1x-UART configured as 1 of:
   RS232 w/ flow-control, RS485, RS422
 - WiFi/BT
 - PCIe Clock generator
 - GPS and accelerometer
 - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S)
 - I/O connector with 2x-ADC,2x-GPIO,1x-UART,1x-I2C
 - wide range power supply

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-11 11:28:54 +08:00