Core changes:
- Minor but nice and important documentation clean-ups.
New drivers:
- New subdriver for the Qualcomm SDM670 SoC.
- New subdriver for the Intel Moorefield SoC.
- New trivial support for the NXP Freescale i.MXRT1170 SoC.
Other changes and improvements
- A major clean-up of the Qualcomm pin control device tree bindings
by Krzysztof.
- A major header clean-up by Andy.
- Some immutable irqchip clean-up for the Actions Semiconductor
and Nuvoton drivers.
- GPIO helpers for The Cypress cy8c95x0 driver.
- Bias handling in the Mediatek MT7986 driver.
- Remove the unused pins-are-numbered concept that never flew.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmOXJjQACgkQQRCzN7AZ
XXOMaxAAuAv30XWa9sq5cMZKOlY3CLudZmxF5V7PSpFwAXiBPcPZu9ajxlaGJaAf
+KOgJhNKYhTb4mBxsQR3X749qFFlxnbEXo9u7ka2bb5bCEkP6ZooqKSGclzAufrp
azf1pmJYd2PoaZzwhpuosiWAzLNTeZBQPapU/d9KFIkNhvvY8dFG8YWrjV6YSMTr
6sPWj7/FCqxAzplrQRUXapS+k5JyihyY4aHcFgJwijN6qmSRCxc49SA4VQvkZQZ3
AP6NV1sX9JvbfgOm09Uk5doBnX4vyfeEshOq/c+XZVyr+ECzlGQARkgOXpPhPA8S
28bY6aDaiu5HzOBauM4bp0Z4W7m7YWKWo1cDZNPVEAMF/oATOj/h3YFhLAy66RtV
8BqEEXKvVwqGu0/utwlB1I+yLXvS0DN9C+TZ2y2aLfkgRHUonRrS1OKa0SSvvQp3
3eXmwTJgqf01bcK7kkdDr6+1H6lRmol27Gir6We5jdOCu0LqQcSIYhCr0RzSirWm
CHIZQTfo7J4S7pOrz7lhsFciqEQeQfsKXmSorLHrVNcGamIZZEdRhEqVxufqRU4B
0hWoNqxjIDcqyZFFUe211OwNWNOUwMdvw5bCVkmhW5e7AylTrOi1ie1b/SlmDxRl
k7NSVnIXdZmog0fYsSZy6qJM0FfTKXF7smnuZcBvgx61/MoCRDw=
=PhTP
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The two large chunks is the header clean-up from Andy and the Qualcomm
DT bindings clean-up from Krzysztof. Each which could give rise to
conflicts, but I haven't seen any.
The YAML conversions happening around the device tree is the biggest
item in the series and is the result of Rob Herrings ambition to
autovalidate these trees against strict schemas and it is paying off
in lots of bugs found and ever prettier device trees. Sooner or later
the transition will be complete, Krzysztof is fixing up all of the
Qualcomm stuff, which is pretty voluminous.
Core changes:
- minor but nice and important documentation clean-ups
New drivers:
- subdriver for the Qualcomm SDM670 SoC
- subdriver for the Intel Moorefield SoC
- trivial support for the NXP Freescale i.MXRT1170 SoC
Other changes and improvements
- major clean-up of the Qualcomm pin control device tree bindings by
Krzysztof
- major header clean-up by Andy
- some immutable irqchip clean-up for the Actions Semiconductor and
Nuvoton drivers
- GPIO helpers for The Cypress cy8c95x0 driver
- bias handling in the Mediatek MT7986 driver
- remove the unused pins-are-numbered concept that never flew"
* tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits)
pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()
dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered
pinctrl: stm32: Remove check for pins-are-numbered
pinctrl: mediatek: common: Remove check for pins-are-numbered
pinctrl: qcom: remove duplicate included header files
pinctrl: sunxi: d1: Add CAN bus pinmuxes
pinctrl: loongson2: Fix some const correctness
pinctrl: pinconf-generic: add missing of_node_put()
pinctrl: intel: Enumerate PWM device when community has a capability
pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
pwm: lpss: Allow other drivers to enable PWM LPSS
pwm: lpss: Include headers we are the direct user of
pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
pwm: Add a stub for devm_pwmchip_add()
pinctrl: k210: call of_node_put()
pinctrl: starfive: Use existing variable gpio
dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching
pinconf-generic: fix style issues in pin_config_param doc
pinctrl: pinctrl-loongson2: fix Kconfig dependency
...
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmN2GBEACgkQb7wzTHR8
rCjfwRAAnG9/iBsiB9jDEbh6ZxNVC+2IAZ4KbaDl3KWhiA8WIbuwV1V2O2YGHXtJ
W8tcHbvvfvr5FOYzxolfx0jiaQX5O5FEt1JKx0GZnqIU6TK6H3SQf7GzYP3DcAQC
RdTy+naHWyJkOz4QI7vFeRIB5AtJJfd8BtyYmBgPiXDlGDBNZes5RP8Stb4aeWjO
QFkyH/wOpkEajPuRQ+muhP40mXAqJWctw7XA0TGMOvnto7RMAmJkv/5RYXBqpGGz
+0mHuFHXrLKUfPTieRrS1HhkYi2Uva6CIqEdhTLxZf2tmL6Qswv7tCUDnjj3ScAJ
b4wQxin82fDitFd+pTmmj1vgpDWKa7rDFKpcIxBu5IsnCLOXm6XTVWroq2pGMhuy
OQLPMXdwj5mnmtSQKx7oxuvrZ4lfGpIJ1p3b3LP9iOE1gIQ3pncKZTDntpDT8hsW
P/gxRTKTNMCNCO17DPPov48wiVzxzBRYp/6H+HQEN+HRBAJNaWNxeY0vuy9o7Jwt
CYHPtUAeBUoj6lNES1QRoacW56dOcvxI5upnoFmNyIQdbp1Vr1izefdpiph/PEG9
4RwlNA/Bl3o34L3KvQZxW7q/b5QSZTA1VPIjroVVZ540B1/s+6p8dXOXLaKic87x
BUmmDIvO//lnAfEW1DQvnKajvYThhi98xttFHxUDfDRQVsE1Hrw=
=4klv
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-1
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
UFS reset pin offsets are wrongly configured for SC8280XP,
correcting the same for both UFS instances here.
Signed-off-by: Anjana Hari <quic_ahari@quicinc.com>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # QDrive3
Link: https://lore.kernel.org/r/20221103181051.26912-1-quic_bjorande@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Previously the cleanup change dropped the bitfield.h from the
pinctrl-lpass-lpi.h, since it's not used there, but forgot to
re-instantiate it in the C-file, where users are located.
Fix this by adding missed bitfield.h to the C-file.
Fixes: aa9430f8a6 ("pinctrl: qcom: Add missing header(s)")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Add missing and remove unused headers in the pin control and GPIO drivers
* Revise the pin control and GPIO headers
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmNX5WAACgkQb7wzTHR8
rChXxw//YFAxU6PSp0tdmgN8U31YpgwfurSENF3B/oDXGumNfmf+e80/W/xjY4GR
lQXYv17CqJFVQKPtgFSZoHF2YvwLeLI0GtKsfQYbcIOqBsnfHULtSGay25axAzmC
2RwTAc9KYgrJuZiSKJjMGqa6HaQRRkw4oxLuFcG60ZuDvbGM/rQXEgoNs297r/IJ
2ra8TJpc9eOgiBzPqy5ahIFP3yWbitk2uYjOduIu+1ngD4knvcPypqfEmMvA2r4J
84Tni7ZzqqtdvQVdIGvhHyDmlgsCaCULQmGz9O/d5k5zmCpR8+UiXO8lto5UGq5T
xY3kyUomFcumVB7VIPjhjIYNHvUIdOB/N0UfFOL0EieULIVRcfqrVSBJZD93Cg+s
YolpMgUDfs99mjyAWhoMi2HgzesKfBYWlUMCgNsK/X0J3u4P/XUA22xdp70A8D5q
E4IYllUGjDxRKfA30XqkFzis+NWaHF0gj5+piIe3RY5OqRfPGnj1H5VgNu5QjFES
kGC3g2+Wu8vfqXl/IEqNntkbnjUDzl+wL7jBNJbtep4440m91tFCmjj5wl8vHHS6
B6/rfx3d/I8aO3kroZz8Pg1KEgjUl0cmTsL+XgOCePaWOKCDmTQeS7h3UhbPRVyd
udig2At3TfO+0w00jYabH2n+VIaIo4gdbQUc9q4NICn/9vuIZ9c=
=gj0F
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v6.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.1-2
* Add missing and remove unused headers in the pin control and GPIO drivers
* Revise the pin control and GPIO headers
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
sdm670_reserved_gpios is only used in pinctrl-sdm670.c now, change it
to static.
Fixes: 61164d220f ("pinctrl: qcom: add sdm670 pinctrl")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20221020075650.1031228-1-yangyingliang@huawei.com
Acked-by: Richard Acayan <mailingradian@gmail.com>
[Fix up subject]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Back in the description of commit e440e30e26 ("arm64: dts: qcom:
sc7180: Avoid glitching SPI CS at bootup on trogdor") we described a
problem that we were seeing on trogdor devices. I'll re-summarize here
but you can also re-read the original commit.
On trogdor devices, the BIOS is setting up the SPI chip select as:
- mux special function (SPI chip select)
- output enable
- output low (unused because we've muxed as special function)
In the kernel, however, we've moved away from using the chip select
line as special function. Since the kernel wants to fully control the
chip select it's far more efficient to treat the line as a GPIO rather
than sending packet-like commands to the GENI firmware every time we
want the line to toggle.
When we transition from how the BIOS had the pin configured to how the
kernel has the pin configured we end up glitching the line. That's
because we _first_ change the mux of the line and then later set its
output. This glitch is bad and can confuse the device on the other end
of the line.
The old commit e440e30e26 ("arm64: dts: qcom: sc7180: Avoid
glitching SPI CS at bootup on trogdor") fixed the glitch, though the
solution was far from elegant. It essentially did the thing that
everyone always hates: encoding a sequential program in device tree,
even if it's a simple one. It also, unfortunately, got broken by
commit b991f8c362 ("pinctrl: core: Handling pinmux and pinconf
separately"). After that commit we did all the muxing _first_ even
though the config (set the pin to output high) was listed first. :(
I looked at ideas for how to solve this more properly. My first
thought was to use the "init" pinctrl state. In theory the "init"
pinctrl state is supposed to be exactly for achieving glitch-free
transitions. My dream would have been for the "init" pinctrl to do
nothing at all. That would let us delay the automatic pin muxing until
the driver could set things up and call pinctrl_init_done(). In other
words, my dream was:
/* Request the GPIO; init it 1 (because DT says GPIO_ACTIVE_LOW) */
devm_gpiod_get_index(dev, "cs", GPIOD_OUT_LOW);
/* Output should be right, so we can remux, yay! */
pinctrl_init_done(dev);
Unfortunately, it didn't work out. The primary reason is that the MSM
GPIO driver implements gpio_request_enable(). As documented in
pinmux.h, that function automatically remuxes a line as a GPIO. ...and
it does this remuxing _before_ specifying the output of the pin. You
can see in gpiod_get_index() that we call gpiod_request() before
gpiod_configure_flags(). gpiod_request() isn't passed any flags so it
has no idea what the eventual output will be.
We could have debates about whether or not the automatic remuxing to
GPIO for the MSM pinctrl was a good idea or not, but at this point I
think there is a plethora of code that's relying on it and I certainly
wouldn't suggest changing it.
Alternatively, we could try to come up with a way to pass the initial
output state to gpio_request_enable() and plumb all that through. That
seems like it would be doable, but we'd have to plumb it through
several layers in the stack.
This patch implements yet another alternative. Here, we specifically
avoid glitching the first time a pin is muxed to GPIO function if the
direction of the pin is output. The idea is that we can read the state
of the pin before we set the mux and make sure that the re-mux won't
change the state.
NOTES:
- We only do this the first time since later swaps between mux states
might want to preserve the old output value. In other words, I
wouldn't want to break a driver that did:
gpiod_set_value(g, 1);
pinctrl_select_state(pinctrl, special_state);
pinctrl_select_default_state();
/* We should be driving 1 even if "special_state" made the pin 0 */
- It's safe to do this the first time since the driver _couldn't_ have
explicitly set a state. In order to even be able to control the GPIO
(at least using gpiod) we have to have requested it which would have
counted as the first mux.
- In theory, instead of keeping track of the first time a pin was set
as a GPIO we could enable the glitch-free behavior only when
msm_pinmux_request_gpio() is in the callchain. That works an enables
my "dream" implementation above where we use an "init" state to
solve this. However, it's nice not to have to do this. By handling
just the first transition to GPIO we can simply let the normal
"default" remuxing happen and we can be assured that there won't be
a glitch.
Before this change I could see the glitch reported on the EC console
when booting. It would say this when booting the kernel:
Unexpected state 1 in CSNRE ISR
After this change there is no error reported.
Note that I haven't reproduced the original problem described in
e440e30e26 ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at
bootup on trogdor") but I could believe it might happen in certain
timing conditions.
Fixes: b991f8c362 ("pinctrl: core: Handling pinmux and pinconf separately")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20221014103217.1.I656bb2c976ed626e5d37294eb252c1cf3be769dc@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various
features. Add a driver to support it.
Link: de5a12173c%5E%21/#F6
Link: 04f083156d%5E%21/#F22
Link: 54837652e3%5E%21/#F0
Link: f0409b0717%5E%21/#F0
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221014001934.4995-4-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It may be necessary for some devices to specify reserved gpios in the
device-specific DTS, in addition to the reserved gpios common to all
devices with a given SoC. Remove this bitmap_fill() call so that the
settings applied to the gpio valid mask by DTS are not overridden by
the driver's reserved gpios.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221014001934.4995-3-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- Cypress CY8C95x0 chip pin control support, along with an immediate
cleanup.
- Mediatek MT8188 SoC pin control support.
- Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem)
pin control support.
- Qualcomm PM7250, PM8450
- Rockchip RV1126 SoC pin control support.
Improvements:
- Fix some missing pins in the Armada 37xx driver.
- Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro.
- Fix some GPIO irq_chips to be immutable.
- Massive Qualcomm device tree binding cleanup, with more to come.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmNEhjMACgkQQRCzN7AZ
XXMNXRAAuqKM8b/Kw7H9S2sBgMuESk2WKe/lmJ6mQCWK1iyo0xecEQi1wN3WGZt1
DfoYHdsB45GWnRcwIVIl2wAjce72EFepCa/sut55TR/bLDxRfSiHGBKatSk5VkQp
IGx75EtsRPgnZCUU3jQgrQEiI8eqj90nr8CugZwD7gocjAtaRJXb0cc3NPyk/TDh
Wyku3rYuzztLCJHwsZ7Q9zh3s9b8Vb43pK9BW8HHeuODqMECaDWTEQUDetKz/Z8X
v7v01PSOafBQUCoFPezz/20kOV9llxFSCeCqbwG3zvjPSjofVwSFoSH1Op4Ybr/t
JWM8Py1+/G/rbsRhZuEahLJ+/eLy7SWABSUq2sxwCEr/VkzNCZ1jKH/qB1S7ZkI6
GcHPbEeCDzcN+yfKIo8p6WHUYivpj2XKXqh/BWIY63rJ3ukrq3WHuJNvCO15F/TJ
PDuLIL0RdNxSanoamsplNtFWA3ap92P2P933k+v06VEZpZys8j/JHFUaysbiqpL+
GoHdRjspFC/4Ob3FwbbiYktpoKmRsZl7PCJSYnnz5nrHFUbQ4LtrgppqMgGXny16
P0pW8IBmIF4yVteodQFsyYZq2yH91TengHleqoFsK0OjYXG0BmRm3lYWLjWbojxe
U7E5T5qQo2rtdVct9d47UznK3IRThDDJx9DtG+Y19VpkKiOy6j8=
=PvLX
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"There is nothing exciting going on, no core changes, just a few
drivers and cleanups.
New drivers:
- Cypress CY8C95x0 chip pin control support, along with an immediate
cleanup
- Mediatek MT8188 SoC pin control support
- Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin
control support
- Qualcomm PM7250, PM8450
- Rockchip RV1126 SoC pin control support
Improvements:
- Fix some missing pins in the Armada 37xx driver
- Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP()
macro
- Fix some GPIO irq_chips to be immutable
- Massive Qualcomm device tree binding cleanup, with more to come"
* tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits)
MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement
pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"
pinctrl: Create subdirectory for StarFive drivers
dt-bindings: pinctrl: st,stm32: Document interrupt-controller property
dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property
dt-bindings: pinctrl: st,stm32: Document gpio-line-names
pinctrl: st: stop abusing of_get_named_gpio()
pinctrl: wpcm450: Correct the fwnode_irq_get() return value check
pinctrl: bcm: Remove unused struct bcm6328_pingroup
pinctrl: qcom: restrict drivers per ARM/ARM64
pinctrl: bcm: ns: Remove redundant dev_err call
gpio: rockchip: request GPIO mux to pinctrl when setting direction
pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback
pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops
pinctrl: cy8c95x0: Drop atomicity on operations on push_pull
pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()
pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper
pinctrl: stm32: Switch to use dev_err_probe() helper
dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings
pinctrl: qcom: spmi-gpio: Add compatible for PM7250B
...
There is no point to allow selecting pin-controller drivers for Qualcomm
ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes
kernel configuration more difficult as many do not remember the Qualcomm
SoCs. There won't be a single image for ARMv7 and ARMv8/9 SoCs, so no
features/options are lost.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220925112103.148836-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SPMI based PMICs have the HIGH and LOW GPIO output strength mappings
interchanged, fix them.
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Link: https://lore.kernel.org/r/20220912210624.4527-3-quic_amelende@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2 and
GPIO_MV_VIN3.
GPIO_LV_VIN2 GPIOs support two input reference voltages: VIN0 and
VIN1. These are typically connected to 1.8 V and 1.2 V supplies
respectively.
GPIO_MV_VIN3 GPIOs support three input reference voltages: VIN0,
VIN1, and VIN2. These are typically connected to Vph, 1.8 V, and
1.2 V supplies respectively.
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Link: https://lore.kernel.org/r/20220912210624.4527-2-quic_amelende@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The irqchip implementation used inside the gpiochips are not supposed to
be changed during runtime. So let's make the one inside the spmi-gpio
gpiochip immutable.
This fixes the below warning during boot:
gpio gpiochip0: (c440000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220830092232.168561-1-manivannan.sadhasivam@linaro.org
[switched two lines as indicated by Johan]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SC8280XP.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8450.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin numbers for UFS_RESET and SDC2_* are not
consistent in the pinctrl driver for sc8180x.
So fix it.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Fixes: 97423113ec ("pinctrl: qcom: Add sc8180x TLMM driver")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220807122645.13830-3-mollysophia379@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently in the wakeirq_map, gpio36 and gpio37 have the same wakeirq
number, resulting in gpio37 being unable to trigger interrupts.
It looks like that this is a typo in the wakeirq map. So fix it.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Fixes: 97423113ec ("pinctrl: qcom: Add sc8180x TLMM driver")
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220807122645.13830-2-mollysophia379@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).
New drivers:
- Intel Meteor Lake support.
- Reneasas RZ/V2M and r8a779g0 (R-Car V4H).
- AXP209 variants AXP221, AXP223 and AXP809.
- Qualcomm MSM8909, PM8226, PMP8074 and SM6375.
- Allwinner D1.
Improvements:
- Proper pin multiplexing in the AMD driver.
- Mediatek MT8192 can use generic drive strength and pin
bias, then fixes on top plus some I2C pin group fixes.
- Have the Allwinner Sunplus SP7021 use the generic DT schema and
make interrupts optional.
- Handle Qualcomm SC7280 ADSP.
- Handle Qualcomm MSM8916 CAMSS GP clock muxing.
- High impedance bias on ZynqMP.
- Serialize StarFive access to MMIO.
- Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmLy1PoACgkQQRCzN7AZ
XXOavA/+O9lIcZqt/I3ZzA4+paEJsXM/win6NKGUHlAE76D5qOvMEXPYCszccGVl
0ZV9s3A3xmlb0AQZONeiK5M6FTghnIHiPMI5Ewzw358hZQg68Mgaba5+/yTqc9ZT
L5zs6whboB1Mlr05L3g5e5ImM1FdFklGHimI6G/evE5r1ZXAAdoyXbSzWgtgLwp9
Gn3rstfqxwwPa9QWIjCXXIeZ/EFnX6BRFT5Pu47dRz/67UWB3xzJjRkZXBf8Nag9
/H/TpmkXSFNaP8HK2kN8m5eNtfWLYM1AmjFPNICWtKLhH12ArD3j+MBYLcJoDnAI
JZryrMSFi2P14Ov42zYeJaSjReTt/QBcRAlWBhSiuotJHl6wrFXzM6wA6JirfvsJ
XQsNm7rKfkmfJ84VjqmCg6QF+39fwKw9MYY9IMXsey7864pBWSyl2xYXUjwXFLua
EWh+6I1CX4db/S6I/uqvluDenT0NKAPZ3rwK5Al1m1DMI47kz0qoW5ZxAW10xeYB
BNGN7IyRvYZhfA/DHcxMB5XgateIKTJqfcYnmHD29Ep4skEetOSac0wVytd3S+Hw
v1zklpcGDLHNiCBXmTYniTlfgBkWJUmVCLA4K6TjSNUKfeoR+33wlpnPHveq8ckn
PJLf79A+5Br3IsLnr6AzDrmtCd0sV46Gy8Vi5I1TD1i/LUUhnL0=
=enmk
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Outside the pinctrl driver and DT bindings we hit some Arm DT files,
patched by the maintainers.
Other than that it is business as usual.
Core changes:
- Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).
New drivers:
- Intel Meteor Lake support.
- Reneasas RZ/V2M and r8a779g0 (R-Car V4H).
- AXP209 variants AXP221, AXP223 and AXP809.
- Qualcomm MSM8909, PM8226, PMP8074 and SM6375.
- Allwinner D1.
Improvements:
- Proper pin multiplexing in the AMD driver.
- Mediatek MT8192 can use generic drive strength and pin bias, then
fixes on top plus some I2C pin group fixes.
- Have the Allwinner Sunplus SP7021 use the generic DT schema and
make interrupts optional.
- Handle Qualcomm SC7280 ADSP.
- Handle Qualcomm MSM8916 CAMSS GP clock muxing.
- High impedance bias on ZynqMP.
- Serialize StarFive access to MMIO.
- Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"
* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
pinctrl: qcom: sm8250: Fix PDC map
pinctrl: amd: Fix an unused variable
dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
dt-bindings: pinctrl: mt8186: Add gpio-line-names property
ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
pinctrl: amd: Use unicode for debugfs output
pinctrl: amd: Fix newline declaration in debugfs output
pinctrl: at91: Fix typo 'the the' in comment
dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
pinctrl: mvebu: Missing a blank line after declarations.
pinctrl: qcom: Add SM6375 TLMM driver
dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
pinctrl: imx93: Add MODULE_DEVICE_TABLE()
pinctrl: sunxi: Add driver for Allwinner D1
pinctrl: sunxi: Make some layout parameters dynamic
pinctrl: sunxi: Refactor register/offset calculation
...
All the many other configs depend on config PINCTRL_MSM, yet for config
PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450
depend on PINCTRL_MSM to be consistent with the rest.
Signed-off-by: John Garry <john.garry@huawei.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a driver to control the TLMM block on SM6375. This is an adapted
version of msm-5.4's pinctrl-blair driver.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The gpiolib is unique in the way it uses intermediate fwspecs
when feeding an interrupt specifier to the parent domain, as it
relies on the populate_parent_alloc_arg() callback to perform
a dynamic allocation.
This is pretty inefficient (we free the structure almost immediately),
and the only reason this isn't a stack allocation is that our
ThunderX friend uses MSIs rather than a FW-constructed structure.
Let's solve it by providing a new type composed of the union
of a struct irq_fwspec and a msi_info_t, which satisfies both
requirements. This allows us to use a stack allocation, and we
can move the handful of users to this new scheme.
Also perform some additional cleanup, such as getting rid of the
stub versions of the irq_domain_translate_*cell helpers, which
are never used when CONFIG_IRQ_DOMAIN_HIERARCHY isn't selected.
Tested on a Tegra186.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Daniel Palmer <daniel@thingy.jp>
Cc: Romain Perier <romain.perier@gmail.com>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Robert Richter <rric@kernel.org>
Cc: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220707182314.66610-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.
Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!
Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the compilation error, caused by updating constant variable.
Hence remove redundant constant variable, which is no more useful
as per new design.
The issue is due to some unstaged changes. Fix it up.
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The idea was right but the code was breaking in next.
I assume some unstaged commit was involed. Fix it up.
Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the
function was never assigned to the pingroup (even though the function
exists already).
Add this mode to the related pins.
Fixes: 5373a2c5ab ("pinctrl: qcom: Add msm8916 pinctrl driver")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update lpass lpi pin control driver, with clock optional check for ADSP
disabled platforms. This check required for distingushing ADSP based
platforms and ADSP bypass platforms.
In case of ADSP enabled platforms, where audio is routed through ADSP
macro and decodec GDSC Switches are triggered as clocks by pinctrl
driver and ADSP firmware controls them. So It's mandatory to enable
them in ADSP based solutions.
In case of ADSP bypass platforms clock voting is optional as these macro
and dcodec GDSC switches are maintained as power domains and operated from
lpass clock drivers.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1654921357-16400-3-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pm6125 has 9 GPIOs with no holes inbetween.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220511220613.1015472-4-marijn.suijten@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-----BEGIN PGP SIGNATURE-----
iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmJu9FYeHHRvcnZhbGRz
QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGAyEH/16xtJSpLmLwrQzG
o+4ToQxSQ+/9UHyu0RTEvHg2THm9/8emtIuYyc/5FgdoWctcSa3AaDcveWmuWmkS
KYcdhfJsaEqjNHS3OPYXN84fmo9Hel7263shu5+IYmP/sN0DfQp6UWTryX1q4B3Q
4Pdutkuq63Uwd8nBZ5LXQBumaBrmkkuMgWEdT4+6FOo1mPzwdIGBxCuz1UsNNl5k
chLWxkQfe2eqgWbYJrgCQfrVdORXVtoU2fGilZUNrHRVGkkldXkkz5clJfapyZD3
odmZCEbrE4GPKgZwCmDERMfD1hzhZDtYKiHfOQ506szH5ykJjPBcOjHed7dA60eB
J3+wdek=
=39Ca
-----END PGP SIGNATURE-----
Merge tag 'v5.18-rc5' into devel
Merge in Linux 5.18-rc5 since new code to the STM32 driver
depend in a non-trivial way on the fixes merged in -rc5.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, as these macro and dcodec GDSC switches are
maintained as power domains and operated from lpass clock drivers.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Prevent gpiolib from messing with the irqchip by advertising
the irq_chip structure as immutable, making it const, and adding
the various calls that gpiolib relies upon.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220419141846.598305-8-maz@kernel.org
In other places the SDC and UFS pins have been swapped but this was
missed in the PINCTRL_PIN definitions. Fix that.
Fixes: 7d74b55afd ("pinctrl: qcom: Add SM6350 pinctrl driver")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20220318183004.858707-5-luca.weiss@fairphone.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Specify the PDC mapping for SM8150, so that gpio interrupts are
properly mapped to the wakeup IRQs of the PDC.
Cc: Maulik Shah <quic_mkshah@quicinc.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220226184028.111566-3-bhupesh.sharma@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
