Commit graph

2423 commits

Author SHA1 Message Date
Paul Gortmaker
4d1db6e783 pinctrl: imx1: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/freescale/Kconfig:config PINCTRL_IMX1
drivers/pinctrl/freescale/Kconfig:	bool "IMX1 pinctrl driver"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-29 09:31:03 +02:00
Paul Gortmaker
7f8750ada0 pinctrl: freescale: remove needless module.h include
None of these files have anything modular in them, so they
don't need to be bringing in module.h and all its dependencies.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-29 09:30:10 +02:00
Linus Walleij
dd032e8dc5 Merge branch 'devel-dt-free-map' into devel 2016-06-23 11:19:14 +02:00
Jon Hunter
8dfebf57bd pinctrl: pinconf: Add generic helper function for freeing mappings
The pinconf-generic.h file exposes functions for creating generic mappings
but it does not expose a function for freeing the mappings. Add a function
for freeing generic mappings.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-23 11:18:56 +02:00
Cristina Ciocan
b41aa4f847 pinctrl: baytrail: Fix mingled clock pins
Fix plt clock 3, 4 and 5 pins, which were not in the proper order.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-23 11:05:04 +02:00
Ramesh Shanmugasundaram
2d77583198 pinctrl: sh-pfc: r8a7795: Add DRIF support
This patch adds DRIF[0-3] pinmux support for r8a7795 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-23 11:01:21 +02:00
Kuninori Morimoto
d07640f576 pinctrl: sh-pfc: r8a7795: Use PINMUX_SINGLE() for I2C
Now we have PINMUX_SINGLE(). Let's use it instead of PINMUX_IPSR_NOGP()

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-23 11:01:11 +02:00
Ben Dooks
a688e3517c pinctrl: rockchip: make rockchip_irq_gc_mask_set_bit static
The rockchip_irq_gc_mask_set_bit() function is not exported our used
outside of ppinctrl-rockchip.c so fix the following sparse error by
making it static:

drivers/pinctrl/pinctrl-rockchip.c:2010:6: warning:
  symbol 'rockchip_irq_gc_mask_set_bit' was not declared.
  Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-23 10:48:28 +02:00
Baruch Siach
828d631783 Revert "pinctrl: digicolor: add missing platform_set_drvdata() call"
This reverts commit 8b2b3dcb34.

Commit 546c6d7930 (pinctrl: digicolor: make it explicitly non-modular) removed
the platform_get_drvdata() call, so platform_set_drvdata() is no longer needed.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-23 09:50:05 +02:00
Paul Gortmaker
9385f35d64 pinctrl: as3722: convert PINCTRL_AS3722 from bool to tristate
The Kconfig currently controlling compilation of this code is:

config PINCTRL_AS3722
        bool "Pinctrl and GPIO driver for ams AS3722 PMIC"

...meaning that it currently is not being built as a module by anyone.

During an audit for non-modular drivers using modular infrastructure
this driver showed up.

But rather than demodularize it, Laxman indicated that it would be
prefereable to instead convert the driver option to tristate.

This does that, and confirms that it will compile and modpost as
such.  However, since I do not have the hardware to confirm that
no new runtime issues exist when modular, that remains untested.

Cc: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 18:09:24 +02:00
Paul Gortmaker
767b8ce361 pinctrl: palmas: convert PINCTRL_PALMAS from bool to tristate
The Kconfig currently controlling compilation of this code is:

config PINCTRL_PALMAS
        bool "Pinctrl driver for the PALMAS Series MFD devices"

...meaning that it currently is not being built as a module by anyone.

During an audit for non-modular drivers using modular infrastructure
this driver showed up.

But rather than demodularize it, Laxman indicated that it would be
prefereable to instead convert the driver option to tristate.

This does that, and confirms that it will compile and modpost as
such.  However, since I do not have the hardware to confirm that
no new runtime issues exist when modular, that remains untested.

Cc: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 18:08:31 +02:00
Axel Lin
19b5a91764 pinctrl: tegra: Fix build dependency
I got below build error:
ERROR: "tegra_xusb_padctl_legacy_probe"
 [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
with below build configuration:
CONFIG_ARCH_TEGRA=y
CONFIG_PINCTRL_TEGRA_XUSB=y
CONFIG_PHY_TEGRA_XUSB=y

The problem is below line in drivers/pinctrl/Makefile
obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/

So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.

phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 17:58:07 +02:00
Tony Lindgren
0ac3c0a402 pinctrl: single: Fix missing flush of posted write for a wakeirq
With many repeated suspend resume cycles, the pin specific wakeirq
may not always work on omaps. This is because the write to enable the
pin interrupt may not have reached the device over the interconnect
before suspend happens.

Let's fix the issue with a flush of posted write with a readback.

Cc: stable@vger.kernel.org
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 17:58:07 +02:00
Alexander Shiyan
ba562d5e54 pinctrl: imx: Do not treat a PIN without MUX register as an error
Some PINs do not have a MUX register, it is not an error.
It is necessary to allow the continuation of the PINs configuration,
otherwise the whole PIN-group will be configured incorrectly.

Cc: stable@vger.kernel.org
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 17:58:06 +02:00
Geert Uytterhoeven
c29e2f2cb6 pinctrl: sh-pfc: Convert to devm_gpiochip_add_data()
This allows to remove the .remove() callback, and all functions and data
it needed for its own bookkeeping.

Suggested-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:58 +02:00
Geert Uytterhoeven
07d36d2908 pinctrl: sh-pfc: Improve core and user API separation
The Renesas Pin Function Controller uses two header files:
  - sh_pfc.h, for use by both core code and SoC-specific drivers,
  - core.h, for internal use by the core code only.

Several SoC-specific drivers include core.h, as they need the sh_pfc
structure, which is passed explicitly to the various SoC-specific
callbacks, and used there.

Hence move its definition from core.h to sh_pfc.h, and remove the
inclusion of core.h from all SoC-specific files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:55 +02:00
Geert Uytterhoeven
9f4ca14e16 pinctrl: sh-pfc: Move SoC-specific forward declarations to sh_pfc.h
With C=1:

    drivers/pinctrl/sh-pfc/pfc-emev2.c:1695:30: warning: symbol 'emev2_pinmux_info' was not declared. Should it be static?
    drivers/pinctrl/sh-pfc/pfc-r8a7779.c:3888:30: warning: symbol 'r8a7779_pinmux_info' was not declared. Should it be static?

Note that there are more warnings on SH.

The sh_pfc_soc_info structure is defined in sh_pfc.h, while all forward
declarations for the SoC-specific versions are in core.h.
Move the forward declarations from core.h to sh_pfc.h to fix this.

Reported-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:39 +02:00
Jon Hunter
98849fa016 pinctrl: OF: Don't create a pinctrl handle if no pinctrl entries exist
When pinctrl_get() is called for a device, it will return a valid handle
even if the device itself has no pinctrl state entries defined in
device-tree. This is caused by the function pinctrl_dt_to_map() which
will return success even if the first pinctrl state, 'pinctrl-0', is not
found in the device-tree node for a device.

According to the pinctrl device-tree binding documentation, pinctrl
states must be numbered starting from 0 and so 'pinctrl-0' should always
be present if a device uses pinctrl and therefore, if 'pinctrl-0' is not
present it seems valid that we should not return a valid pinctrl handle.

Fix this by returning an error code if the property 'pinctrl-0' is not
present for a device.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:40:15 +02:00
Mika Westerberg
1a7d1cb81e pinctrl: intel: Prevent force threading of the interrupt handler
The pinctrl-intel needs to use request_irq() instead of chained interrupt
handling because it shares the interrupt with multiple GPIO host
controllers found on Intel CPUs. In -rt all such interrupts are forced to
run in thread context which triggers following warning:

 WARNING: CPU: 0 PID: 530 at kernel/irq/handle.c:151 handle_irq_event_percpu+0x23d/0x240
 irq 348 handler irq_default_primary_handler+0x0/0x10 enabled interrupts
 Modules linked in:
 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257c98 ffffffff812d8494 ffff88007a257ce8
  0000000000000000 ffff88007a257cd8 ffffffff8105e554 000000977a257d90
  ffff88007a37a380 000000000000015c 0000000000000002 0000000000000000
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff8105e554>] __warn+0xe4/0x100
  [<ffffffff8105e5bf>] warn_slowpath_fmt+0x4f/0x60
  [<ffffffff810b18f0>] ? __synchronize_hardirq+0x60/0x60
  [<ffffffff810b17fd>] handle_irq_event_percpu+0x23d/0x240
  [<ffffffff810b1862>] handle_irq_event+0x62/0x90
  [<ffffffff810b4e1f>] handle_edge_irq+0x8f/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The handle_irq_event_* functions (and I suppose generic_handle_irq()) is
expected to be called with interrupts disabled and they rightfully complain
here because we run in thread context with interrupts enabled.

Fix this by adding IRQF_NO_THREAD flag when the master interrupt is
requested. This prevents forced threading of the interrupt used by the GPIO
host controllers.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:35:47 +02:00
Mika Westerberg
27d9098cff pinctrl: intel: Use raw_spinlock for locking
When running -rt kernel and GPIO interrupt happens we get following

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
 in_atomic(): 1, irqs_disabled(): 0, pid: 530, name: irq/14-INT3452:
 Preemption disabled at:[<ffffffff810b4dab>] handle_edge_irq+0x1b/0x190

 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257d58 ffffffff812d8494 0000000000000000
  ffff88017a330000 ffff88007a257d78 ffffffff81083a11 ffff88007a252430
  ffff88007a252430 ffff88007a257d90 ffffffff8167ef20 000000000000001a
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff81083a11>] ___might_sleep+0xe1/0x160
  [<ffffffff8167ef20>] rt_spin_lock+0x20/0x50
  [<ffffffff81308c6d>] intel_gpio_irq_ack+0x2d/0x80
  [<ffffffff810b4e0b>] handle_edge_irq+0x7b/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The reason why this happens is because intel_gpio_irq_ack() is called with
desc->lock raw_spinlock locked which cannot sleep but our normal spinlock
(which is converted to rtmutex in -rt) is allowed to sleep. This causes
might_sleep() to trigger.

Fix this by converting the normal spinlock to a raw_spinlock.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:35:44 +02:00
Masahiro Yamada
53501c9771 pinctrl: uniphier: fix meaningless drive control offsets
These are input-only pins.  They do not support drive controlling
in the first place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:03:09 +02:00
Masahiro Yamada
96c8b6903d pinctrl: uniphier: prohibit drive control for pin 61-66 of PH1-LD11
According to the hardware document, setting the drive control is
prohibited for these pins (N-channel Open Drain pins).  Set their
drive control attribute to "fixed".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-18 10:02:09 +02:00
Tan Jui Nee
0c3013bbe1 pinctrl/broxton: enable platform device in the absence of ACPI enumeration
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.

Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:42 +02:00
Arnd Bergmann
79f28b9fcd pinctrl: max77620: select PINMUX
The recently added max77620 driver fails to build when CONFIG_PINMUX
is not set:

pinctrl/pinctrl-max77620.c:272:21: error: variable 'max77620_pinmux_ops' has initializer but incomplete type
 static const struct pinmux_ops max77620_pinmux_ops = {
                     ^~~~~~~~~~
pinctrl/pinctrl-max77620.c:273:2: error: unknown field 'get_functions_count' specified in initializer

This adds the Kconfig 'select' statement that was clearly meant
to be there and is used in all other pinmux drivers.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:41 +02:00
Arnd Bergmann
56411f3c05 pinctrl: fix incorrect inline keyword in multiple drivers
When building with 'make W=1', we get harmless warnings about
five drivers in drivers/pinctrl, which all contain a copy of
the same line:

drivers/pinctrl/freescale/pinctrl-imx1-core.c:160:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration]

This replaces the somewhat nonstandard 'static const inline'
with 'static inline const', which has the same meaning but
does not cause this warning.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:41 +02:00
Jon Hunter
648eb7a1bc pinctrl: max77620: Remove unused structure definition
The strucuture 'max77620_cfg_param' is defined but never used by the
max77620 driver. Remove this structure definition.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:40 +02:00
Dan O'Donovan
77401d7fdf pinctrl: cherryview: add handlers for pin_config_group_get/set
Pin config get/set handlers for pin groups were previously not
implemented by this driver.  The pin_config_group_set is
particularly useful for applying a common config setting to all
pins in a specified group with a single call, without the caller
needing to reference each individual pin by name.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:40 +02:00
Dan O'Donovan
ccdf81d08d pinctrl: cherryview: add option to set open-drain pin config
On some CHV platforms, we need an option to configure the
open-drain setting for these pins.  This adds support for the
PIN_CONFIG_DRIVE_PUSH_PULL and PIN_CONFIG_DRIVE_OPEN_DRAIN to
disable/enable open-drain mode for a specific pin.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:39 +02:00
Dan O'Donovan
0bd50d719b pinctrl: cherryview: prevent concurrent access to GPIO controllers
Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:39 +02:00
Linus Walleij
38c1e5e7b9 pinctrl: qcom-ssbi: support for PM8058
The PM8058 is found in connection to the APQ8060 on the APQ8060
Dragonboard. Works the same as all others, just add the compatible
string for this variant.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-15 08:37:31 +02:00
Geert Uytterhoeven
6f6fca0ab0 pinctrl: sh-pfc: sh7757: Fix duplicate initializer in GPIO pinmux data
With C=1:

    drivers/pinctrl/sh-pfc/pfc-sh7757.c:1613:9: warning: Initializer entry defined twice
    drivers/pinctrl/sh-pfc/pfc-sh7757.c:1628:9:   also defined here

Remove the duplicate initializer to fix this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-06-14 09:41:41 +02:00
Amitoj Kaur Chawla
6b4316aece pinctrl: xway: Change structure initialisation to c99 style
Replace the in order struct initialisation style with explicit field
style.

The Coccinelle semantic patch used to make this change is as follows:

@decl@
identifier i1,fld;
type T;
field list[n] fs;
@@

struct i1 {
 fs
 T fld;
 ...};

@@
identifier decl.i1,i2,decl.fld;
expression e;
position bad.p, bad.fix;
@@

struct i1 i2@p = { ...,
+ .fld = e
- e@fix
 ,...};

Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 14:03:18 +02:00
Ben Dooks
3fed681012 pinctrl: u300: make u300_pmx_registers static
The array u300_pmx_registers is not declared or used outside
of the driver, so make it static to avoid the following warning:

drivers/pinctrl/pinctrl-u300.c:673:11: warning: symbol 'u300_pmx_registers' was not declared. Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 09:27:43 +02:00
Florian Fainelli
f886031f65 pinctrl: Always recurse into bcm folder
drivers/pinctrl/bcm/Makefile properly builds individual drivers based on
their respective Kconfig symbols. ARCH_BCM is currently a menuconfig
option from arch/arm/mach-bcm/Kconfig, which is fine, but prevents ARM64
platforms which do not have such menuconfig option from building their
pinctrl drivers, so let's get rid of that dependency.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 09:25:31 +02:00
Ben Dooks
27cdb5d0fd pinctrl: nomadik: fix warnings from unexported functions
There are five functions in the driver that are defined but
only used locally. Since these are not used in the current
kernel, delete them to avoid the following warnings:

drivers/pinctrl/nomadik/pinctrl-nomadik.c:1036:6: warning: symbol 'nmk_gpio_clocks_enable' was not declared. Should it be static?
drivers/pinctrl/nomadik/pinctrl-nomadik.c:1050:6: warning: symbol 'nmk_gpio_clocks_disable' was not declared. Should it be static?
drivers/pinctrl/nomadik/pinctrl-nomadik.c:1073:6: warning: symbol 'nmk_gpio_wakeups_suspend' was not declared. Should it be static?
drivers/pinctrl/nomadik/pinctrl-nomadik.c:1094:6: warning: symbol 'nmk_gpio_wakeups_resume' was not declared. Should it be static?
drivers/pinctrl/nomadik/pinctrl-nomadik.c:1120:6: warning: symbol 'nmk_gpio_read_pull' was not declared. Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:50:13 +02:00
Paul Gortmaker
f703851af0 pinctrl: at91-pio4: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/Kconfig:config PINCTRL_AT91PIO4
drivers/pinctrl/Kconfig:        bool "AT91 PIO4 pinctrl driver"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:40:14 +02:00
Paul Gortmaker
546c6d7930 pinctrl: digicolor: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/Kconfig:config PINCTRL_DIGICOLOR
drivers/pinctrl/Kconfig:        bool

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:32:19 +02:00
Paul Gortmaker
4c3deee95f pinctrl: zynq: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

config PINCTRL_ZYNQ
        bool "Pinctrl driver for Xilinx Zynq"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:30:58 +02:00
Paul Gortmaker
b8c2b10a9b pinctrl: amd: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

config PINCTRL_AMD
        bool "AMD GPIO pin control"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Ken Xue <Ken.Xue@amd.com>
Cc: Jeff Wu <Jeff.Wu@amd.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:29:20 +02:00
Paul Gortmaker
82359b0ab7 pinctrl: lpc18xx: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

config PINCTRL_LPC18XX
        bool "NXP LPC18XX/43XX SCU pinctrl driver"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Joachim Eastwood <manabian@gmail.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:28:18 +02:00
Paul Gortmaker
eaa864a19e pinctrl: at91: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/Kconfig:config PINCTRL_AT91
drivers/pinctrl/Kconfig:        bool "AT91 pinctrl driver"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init was not being used in this driver, we don't need
to be concerned with initcall ordering changes when removing it.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:27:23 +02:00
Paul Gortmaker
360943a8d2 pinctrl: baytrail: make it explicitly non-modular
The Kconfig currently controlling compilation of this code is:

config PINCTRL_BAYTRAIL
        bool "Intel Baytrail GPIO pin control"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_init() was already not in use in this driver, we don't
have any concerns with init ordering changes here.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 08:25:56 +02:00
Wolfram Sang
e9eace3220 pinctrl: sh-pfc: r8a7795: add support for voltage switching
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-10 09:00:22 +02:00
Wolfram Sang
8775306dcf pinctrl: sh-pfc: refactor voltage setting
All known hardware being able to switch voltages has the same POCCTRL
register. So, factor out the common code to the core and keep only
the pin-to-bit mapping SoC specific. Convert the only user, r8a7790.
In case POCCTRL should ever get more complex (more voltages to select?),
we should probably switch over to a describing array like drive strength
does currently.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-10 09:00:19 +02:00
Ben Dooks
682d68b882 pinctrl: at91-pio4: fix non-exported functions
The atmel_pctl_find_group_by_pin() and the atmel_pinctrl_remove()
functions are not exported, so fix the warnings about these
being exported without definitions by making them static.

drivers/pinctrl/pinctrl-at91-pio4.c:424:20: warning: symbol 'atmel_pctl_find_group_by_pin' was not declared. Should it be static?
drivers/pinctrl/pinctrl-at91-pio4.c:1077:5: warning: symbol 'atmel_pinctrl_remove' was not declared. Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08 14:09:58 +02:00
Ben Dooks
d5e4d7ab2c pinctrl: nsp-gpio: fix non-static functions
Fixup warnings from functions that are not exported and
therefore should be marked static. Fixes:

drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:461:5:
  warning: symbol 'nsp_pin_config_group_get' was not declared.
  Should it be static?
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:467:5:
  warning: symbol 'nsp_pin_config_group_set' was not declared.
  Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08 14:09:49 +02:00
Masahiro Yamada
9467f5688b pinctrl: uniphier: fix NAND pin-mux settings for PH1-LD11/LD20
My mistake in the initial support patches.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08 11:13:11 +02:00
hongkun.cao
d2fcd62a9c pinctrl: mediatek: fix suspend/resume timing issue
An irq which is a wake up source maybe masked unexpectedly if the wake
up source irq was triggered after pinctrl irqchip suspend and before
suspend_device_irqs finished.
Use *_noirq callbacks to guarantee pinctrl irqchip suspend would be
called after suspend_devices_irqs.

Signed-off-by: hongkun.cao <hongkun.cao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08 10:09:40 +02:00
Linus Walleij
86ede3d41b pinctrl: xway: use devm_gpiochip_add_data()
Avoid a gpiochip_free() and use standard functions.

Cc: John Crispin <blogic@openwrt.org>
Cc: Pramod Gurav <pramod.gurav@smartplayin.com>
Cc: Martin Schiller <mschiller@tdt.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-07 09:37:21 +02:00
Neil Armstrong
4d6ddd3b22 pinctrl: oxnas: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map
Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, introduced in
d32f7fd3bb ("pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map")
but not reported into oxnas driver.

Fixes: 611dac1e48 ("pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:59:29 +02:00
Masahiro Yamada
336306ee1f pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:57:45 +02:00
Masahiro Yamada
70f2f9c4cf pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD11 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:56:25 +02:00
Masahiro Yamada
3e030b0b4e pinctrl: uniphier: allow to have pinctrl node under syscon node
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.

To allow to migrate to the new DT structure, this commit adds new
compatible strings to not disturb the existing DT.  After a while,
the old binding will be removed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:54:14 +02:00
Masahiro Yamada
a2456a77ab pinctrl: uniphier: add System Bus pin-mux settings
This is needed to get access to UniPhier System Bus (external bus).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:53:06 +02:00
Masahiro Yamada
1e359ebe33 pinctrl: uniphier: add dedicated pins to pin tables of PH1-LD4/sLD8
These pins do not support pin-muxing, but it is useful to support
pin configuration for them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:52:09 +02:00
Masahiro Yamada
39ec9ace7a pinctrl: uniphier: support pin configuration for dedicated pins
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:50:47 +02:00
Masahiro Yamada
aa543888ca pinctrl: uniphier: support per-pin input enable for new SoCs
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin.  (While, existing ones only support it
per pin-group.)  This commit updates the core part for that.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:49:48 +02:00
Masahiro Yamada
c2ebf4754b pinctrl: uniphier: introduce capability flag
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding the new one.  Having just one flag would be
better than adding a new struct member every time a new SoC-specific
capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from a customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:48:28 +02:00
Masahiro Yamada
94bf176b97 pinctrl: uniphier: support pin configuration in sparse pin space
Unfortunately, the pin number of the new SoC, PH1-LD11, is not
contiguous.  The base frame work must be adjusted to support the new
SoC pinctrl driver.  The pin_desc_get() exploits radix-tree for pin
look-up, so it works more efficiently with sparse pin space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:47:18 +02:00
Masahiro Yamada
72e5706aa7 pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control.  Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:46:18 +02:00
Masahiro Yamada
9eaa98a63c pinctrl: uniphier: rename macros for drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control.  Some of the configuration registers on it have
3-bit width.

The feature will be supported in the next commit, but a problem is
that macro names are getting longer and longer in the current naming
scheme.

Before moving forward, this commit renames macros as follows:

  UNIPHIER_PIN_DRV_4_8        -> UNIPHIER_PIN_DRV_1BIT
  UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT
  UNIPHIER_PIN_DRV_FIXED_4    -> UNIPHIER_PIN_DRV_FIXED4
  UNIPHIER_PIN_DRV_FIXED_5    -> UNIPHIER_PIN_DRV_FIXED5
  UNIPHIER_PIN_DRV_FIXED_8    -> UNIPHIER_PIN_DRV_FIXED8

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:42:04 +02:00
Masahiro Yamada
fc78a56631 pinctrl: uniphier: allocate struct pinctrl_desc in probe function
Currently, every SoC driver defines struct pinctrl_desc statically,
i.e. it consumes memory footprint even if it is not probed.

In multi-platform, many pinctrl drivers are linked (generally as
built-in objects), although only one of them is actually used.
So, it is reasonable to allocate memory dynamically where possible.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:40:38 +02:00
Masahiro Yamada
4109508a85 pinctrl: uniphier: set pinctrl_desc name in common probe function
Every SoC driver sets the same name for struct pinctrl_desc and
platform_driver.  The common probe function can set desc->name
instead of duplicating strings in each SoC driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:39:31 +02:00
Masahiro Yamada
7d36b2451a pinctrl: uniphier: set pinctrl_desc owner in common probe function
The owner of the struct pinctrl_desc matches that of platform_driver.
Set it in the common probe function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:38:30 +02:00
Masahiro Yamada
4725774f59 pinctrl: uniphier: fix register offsets for drive strength control
These pin tables were generated by parsing hardware documents with
a script, but the script had a bug.  Fix the register offsets.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:37:34 +02:00
Masahiro Yamada
a4c6052bc1 pinctrl: uniphier: rename function and variable names
Make function/variable names match the file names for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:36:12 +02:00
Masahiro Yamada
10ef8277ec pinctrl: uniphier: fix .pin_dbg_show() callback
Without this, reading the "pins" in the debugfs causes kernel BUG.

Fixes: 6e90889202 ("pinctrl: UniPhier: add UniPhier pinctrl core support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:56:16 +02:00
Peng Fan
6e408ed8be pinctrl: imx: fix initialization of imx_pinctrl_desc
To i.MX7D, there are two iomux controllers, iomuxc and iomuxc_lpsr.
They should not share one pin controller descriptor, otherwise
the value filled into imx_pinctrl_desc when probing the first
iomux controller will be overridden when probing the second one.

In this patch, discard the static allcoated imx_pinctrl_desc and
switch to dynamically allcate pin controller descriptor for each
iomux controller.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:54:31 +02:00
Kevin Hilman
a454c67d1f pinctrl: amlogic: gxbb: add ethernet pins
Add EE domain pins for ethernet interface.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:37:09 +02:00
Kevin Hilman
6db0f3a8a0 pinctrl: amlogic: gxbb: add more UART pins
Add EE domain pins for UART A, B & C.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:36:17 +02:00
Kevin Hilman
93ed09e6b6 pinctrl: amlogic: gxbb: add EMMC and SD pins
Add EE domain pins for eMMC and SD card.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:35:25 +02:00
Kevin Hilman
a7db188943 pinctrl: amlogic: gxbb: add UART_AO_B, I2C
Add pins for some more AO domain devices: UART_AO_B and I2C master &
slave.

Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:34:36 +02:00
Masahiro Yamada
1fb1f0540d pinctrl: return -ENOMEM instead of -EINVAL for kasprintf() failure
-ENOMEM is more suitable error code because kasprintf() fails
in case of memory shortage.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:33:00 +02:00
Masahiro Yamada
8b2b3dcb34 pinctrl: digicolor: add missing platform_set_drvdata() call
gc_pinctrl_remove() calls platform_get_drvdata(), but I see neither
platform_set_drvdata() nor dev_set_drvdata() anywhere in this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:30:38 +02:00
Masahiro Yamada
a672eb5e27 pinctrl: pinconf: separate config parameters with commas for debugfs
To improve debugfs readability, use commas instead of whitespaces
for separating configuration parameters.

For example, the "pinconf-pins" dump on my board will change as follows:

Without this commit:

 # head -5 pinconf-pins
 Pin config settings per pin
 Format: pin (name): configs
 pin 0 (ED0): input bias pull down output drive strength (8 mA) input enabled
 pin 1 (ED1): input bias pull down output drive strength (8 mA) input enabled
 pin 2 (ED2): input bias pull down output drive strength (8 mA) input enabled

With this commit:

 # head -5 pinconf-pins
 Pin config settings per pin
 Format: pin (name): configs
 pin 0 (ED0): input bias pull down, output drive strength (8 mA), input enabled
 pin 1 (ED1): input bias pull down, output drive strength (8 mA), input enabled
 pin 2 (ED2): input bias pull down, output drive strength (8 mA), input enabled

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:29:06 +02:00
Masahiro Yamada
cd8f61f1e5 pinctrl: copy per-pin driver private data to struct pin_desc
Currently, struct pinctrl_pin_desc can have per-pin driver private
data, but it is not copied to struct pin_desc.

For a driver with sparse pin space, for-loop search like below would
be necessary in order to get the driver-specific data for a desired
pin number.

  for (i = 0; i < pctldev->desc->npins; i++)
          if (pin_number == pctldev->desc->pins[i].number)
                  return pctldev->desc->pins[i].drv_data;

This is not efficient for a driver with a large number of pins.
So, copy the data to struct pin_desc when each pin is registered
for the faster radix tree lookup.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:27:19 +02:00
Masahiro Yamada
cf9d994dcf pinctrl: do not care about blank pin name
If a pin name is not specified in struct pinctrl_pin_desc,
pinctrl_register_one_pin() dynamically assigns its name.
So, desc->name is always a valid pointer here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:19:56 +02:00
hongkun.cao
5edf673d07 pinctrl: mediatek: fix dual-edge code defect
When a dual-edge irq is triggered, an incorrect irq will be reported on
condition that the external signal is not stable and this incorrect irq
has been registered.
Correct the register offset.

Cc: stable@vger.kernel.org
Signed-off-by: Hongkun Cao <hongkun.cao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:13:45 +02:00
Patrice Chotard
4fac724fd7 pinctrl: stm32: factorize stm32_pconf_input/output_get()
As these 2 functions code are 95% similar, factorize them.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 10:06:12 +02:00
Linus Walleij
6b1a7c9ecd pinctrl: nomadik: fix inversion of gpio direction
The input/output directions were inversed on the GPIO direction
read function. Loose a ! and it is correct.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:42:37 +02:00
Krzysztof Kozlowski
a0ee2ac039 pinctrl: samsung: Suppress unbinding to prevent theoretical attacks
Although unbinding a pinctrl driver requires root privileges but it
still might be used theoretically in certain attacks (by triggering NULL
pointer exception or memory corruption).

Samsung pincontrol drivers are essential for system operation so their
removal is not expected. They do not implement remove() driver callback
and they are not buildable as modules.

Suppression of the unbinding will prevent triggering NULL pointer
exception like this (Odroid XU3):

  $ echo 13400000.pinctrl > /sys/bus/platform/drivers/samsung-pinctrl/unbind
  $ cat /sys/kernel/debug/gpio

  Unable to handle kernel NULL pointer dereference at virtual address 00000c44
  pgd = ec41c000
  [00000c44] *pgd=6d448835, *pte=00000000, *ppte=00000000
  Internal error: Oops: 17 [#1] PREEMPT SMP ARM
    (samsung_gpio_get) from [<c034f9a0>] (gpiolib_seq_show+0x1b0/0x26c)
    (gpiolib_seq_show) from [<c01fb8c0>] (seq_read+0x304/0x4b8)
    (seq_read) from [<c02dbc78>] (full_proxy_read+0x4c/0x64)
    (full_proxy_read) from [<c01d9fb0>] (__vfs_read+0x2c/0x110)
    (__vfs_read) from [<c01db400>] (vfs_read+0x8c/0x110)
    (vfs_read) from [<c01db4c4>] (SyS_read+0x40/0x8c)
    (SyS_read) from [<c01078c0>] (ret_fast_syscall+0x0/0x3c)

Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:49 +02:00
Neil Armstrong
2f94ced704 pinctrl: oxnas: Add GPIO get_direction
Implement a get_direction callback for the OXNAS GPIO driver in order
to have pin output polarity in debugfs and new userspace ABI.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:48 +02:00
Laxman Dewangan
2df723d49c pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.

Add pin control driver to configure these parameters through
pin control APIs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:47 +02:00
Laxman Dewangan
b47fca5148 pinctrl: tegra: Get rid of parked_reg
Remove the use of parked_reg and use parked_bit for to know
whether field is supported or not.

This is fix for the patch
commit 1d18a3f0f0
"pinctrl: tegra: avoid parked_reg and parked_bank

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:46 +02:00
Linus Walleij
0bde4897d3 Revert "Revert "pinctrl: tegra: avoid parked_reg and parked_bank""
This reverts commit 0d5358330c.
2016-05-30 09:41:45 +02:00
Neil Armstrong
611dac1e48 pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver
Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:45 +02:00
Andrew Morton
bbccb9c7bb drivers/pinctrl/intel/pinctrl-baytrail.c: fix build with gcc-4.4
gcc-4.4 and thereabouts has issues with initializers of anonymous
unions, and it generates the following warnings:

  drivers/pinctrl/intel/pinctrl-baytrail.c:413: error: unknown field 'simple_funcs' specified in initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: missing braces around initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: (near initialization for 'byt_score_groups[0].<anonymous>')
  drivers/pinctrl/intel/pinctrl-baytrail.c:415: error: unknown field 'simple_funcs' specified in initializer
  drivers/pinctrl/intel/pinctrl-baytrail.c:417: error: unknown field 'simple_funcs' specified in initializer
  ...

Work around this.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-26 15:35:44 -07:00
Linus Torvalds
a37571a29e Pin control bulk changes for the v4.7 kernel cycle:
Core changes:
 
 - Add the devm_pinctrl_register() API and switch all applicable drivers
   to use it, saving lots of lines of code all over the place.
 
 New drivers:
 
 - New driver for the Broadcom NS2 SoC.
 
 - New subdriver for the PXA25x SoCs.
 
 - New subdriver for the AMLogic Meson GXBB SoC.
 
 Driver improvements:
 
 - The Intel Baytrail driver now properly supports pin control.
 
 - The Nomadik, Rockchip, Broadcom BCM2835 supports the .get_direction() callback in
   the GPIO portions.
 
 - Continued development and stabilization of several SH-PFC
   SoC subdrivers: r8a7795, r8a7790, r8a7794 etc.
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Merge tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This kernel cycle was quite calm when it comes to pin control and
  there is really just one major change, and that is the introduction of
  devm_pinctrl_register() managed resources.

  Apart from that linear development, details below.

  Core changes:

   - Add the devm_pinctrl_register() API and switch all applicable
     drivers to use it, saving lots of lines of code all over the place.

  New drivers:

   - driver for the Broadcom NS2 SoC

   - subdriver for the PXA25x SoCs

   - subdriver for the AMLogic Meson GXBB SoC

  Driver improvements:

   - the Intel Baytrail driver now properly supports pin control

   - Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction()
     callback in the GPIO portions

   - continued development and stabilization of several SH-PFC SoC
     subdrivers: r8a7795, r8a7790, r8a7794 etc"

* tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits)
  Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
  pinctrl: meson: Fix eth_tx_en bit index
  pinctrl: tegra: avoid parked_reg and parked_bank
  pinctrl: tegra: Correctly check the supported configuration
  pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
  pinctrl: rockchip: fix pull setting error for rk3399
  pinctrl: stm32: Implement .pin_config_dbg_show()
  pinctrl: nomadik: hide nmk_gpio_get_mode when unused
  pinctrl: ns2: rename pinctrl_utils_dt_free_map
  pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable
  pinctrl: at91: Make at91_gpio_template const
  pinctrl: baytrail: fix some error handling in debugfs
  pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC
  pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged
  pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove()
  pinctrl: nomadik: implement .get_direction()
  pinctrl: nomadik: use BIT() with offsets consequently
  pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range
  pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration
  pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration
  ...
2016-05-19 12:50:56 -07:00
Linus Torvalds
4a5219edcd ARM: SoC driver updates for v4.7
Driver updates for ARM SoCs, these contain various things that touch
 the drivers/ directory but got merged through arm-soc for practical
 reasons. For the most part, this is now related to power management
 controllers, which have not yet been abstracted into a separate
 subsystem, and typically require some code in drivers/soc or arch/arm
 to control the power domains.
 
 Another large chunk here is a rework of the NVIDIA Tegra USB3.0
 support, which was surprisingly tricky and took a long time to
 get done.
 
 Finally, reset controller handling as always gets merged through here
 as well.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs, these contain various things that touch
  the drivers/ directory but got merged through arm-soc for practical
  reasons.

  For the most part, this is now related to power management
  controllers, which have not yet been abstracted into a separate
  subsystem, and typically require some code in drivers/soc or arch/arm
  to control the power domains.

  Another large chunk here is a rework of the NVIDIA Tegra USB3.0
  support, which was surprisingly tricky and took a long time to get
  done.

  Finally, reset controller handling as always gets merged through here
  as well"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits)
  arm-ccn: Enable building as module
  soc/tegra: pmc: Add generic PM domain support
  usb: xhci: tegra: Add Tegra210 support
  usb: xhci: Add NVIDIA Tegra XUSB controller driver
  dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support
  dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding
  PCI: tegra: Support per-lane PHYs
  dt-bindings: pci: tegra: Update for per-lane PHYs
  phy: tegra: Add Tegra210 support
  phy: Add Tegra XUSB pad controller support
  dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
  dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding
  phy: core: Allow children node to be overridden
  clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
  drivers: firmware: psci: make two helper functions inline
  soc: renesas: rcar-sysc: Add support for R-Car H3 power areas
  soc: renesas: rcar-sysc: Add support for R-Car E2 power areas
  soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas
  soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas
  soc: renesas: rcar-sysc: Add support for R-Car H2 power areas
  ...
2016-05-18 13:14:02 -07:00
Linus Torvalds
1eccc6e152 This is the bulk of GPIO changes for kernel cycle v4.7:
Core infrastructural changes:
 
 - Support for natively single-ended GPIO driver stages. This
   means that if the hardware has registers to configure open
   drain or open source configuration, we use that rather than
   (as we did before) try to emulate it by switching the line
   to an input to get high impedance. This is also documented
   throughly in Documentation/gpio/driver.txt for those of you
   who did not understand one word of what I just wrote.
 
 - Start to do away with the unnecessarily complex and
   unitelligible ARCH_REQUIRE_GPIOLIB and
   ARCH_WANT_OPTIONAL_GPIOLIB, another evolutional artifact from
   the time when the GPIO subsystem was unmaintained. Archs can
   now just select GPIOLIB and be done with it, cleanups to
   arches will trickle in for the next kernel. Some minor archs
   ACKed the changes immediately so these are included in this
   pull request.
 
 - Advancing the use of the data pointer inside the GPIO device
   for storing driver data by switching the PowerPC, Super-H
   Unicore and a few other subarches or subsystem drivers in
   ALSA SoC, Input, serial, SSB, staging etc to use it.
 
 - The initialization now reads the input/output state of the
   GPIO lines, so that each GPIO descriptor knows - if this
   callback is implemented - whether the line is input or
   output. This also reflects nicely in userspace "lsgpio".
 
 - It is now possible to name GPIO producer names, line names,
   from the device tree. (Platform data has been supported for
   a while.) I bet we will get a similar mechanism for ACPI
   one of those days. This makes is possible to get sensible
   producer names for e.g. GPIO rails in "lsgpio" in userspace.
 
 New drivers:
 
 - New driver for the Loongson1.
 
 - The XLP driver now supports Broadcom Vulcan ARM64.
 
 - The IT87 driver now supports IT8620 and IT8628.
 
 - The PCA953X driver now supports Galileo Gen2.
 
 Driver improvements:
 
 - MCP23S08 was switched to use the gpiolib irqchip helpers and
   now also suppors level-triggered interrupts.
 
 - 74x164 and RCAR now supports the .set_multiple() callback
 
 - AMDPT was converted to use generic GPIO.
 
 - TC3589x, TPS65218, SX150X, F7188X, MENZ127, VX855, WM831X, WM8994
   support the new single ended callback for open drain
   and in some cases open source.
 
 - Implement the .get_direction() callback for a few more drivers
   like PL061, Xgene.
 
 Cleanups:
 
 - Paul Gortmaker combed through the drivers and de-modularized
   those who are not really modules.
 
 - Move the GPIO poweroff DT bindings to the power subdir where
   they belong.
 
 - Rename gpio-generic.c to gpio-mmio.c, which is much more to the
   point. That's what it is handling, nothing more, nothing less.
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Merge tag 'gpio-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of GPIO changes for kernel cycle v4.7:

  Core infrastructural changes:

   - Support for natively single-ended GPIO driver stages.

     This means that if the hardware has registers to configure open
     drain or open source configuration, we use that rather than (as we
     did before) try to emulate it by switching the line to an input to
     get high impedance.

     This is also documented throughly in Documentation/gpio/driver.txt
     for those of you who did not understand one word of what I just
     wrote.

   - Start to do away with the unnecessarily complex and unitelligible
     ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB, another
     evolutional artifact from the time when the GPIO subsystem was
     unmaintained.

     Archs can now just select GPIOLIB and be done with it, cleanups to
     arches will trickle in for the next kernel.  Some minor archs ACKed
     the changes immediately so these are included in this pull request.

   - Advancing the use of the data pointer inside the GPIO device for
     storing driver data by switching the PowerPC, Super-H Unicore and
     a few other subarches or subsystem drivers in ALSA SoC, Input,
     serial, SSB, staging etc to use it.

   - The initialization now reads the input/output state of the GPIO
     lines, so that each GPIO descriptor knows - if this callback is
     implemented - whether the line is input or output.  This also
     reflects nicely in userspace "lsgpio".

   - It is now possible to name GPIO producer names, line names, from
     the device tree.  (Platform data has been supported for a while).
     I bet we will get a similar mechanism for ACPI one of those days.
     This makes is possible to get sensible producer names for e.g.
     GPIO rails in "lsgpio" in userspace.

  New drivers:

   - New driver for the Loongson1.

   - The XLP driver now supports Broadcom Vulcan ARM64.

   - The IT87 driver now supports IT8620 and IT8628.

   - The PCA953X driver now supports Galileo Gen2.

  Driver improvements:

   - MCP23S08 was switched to use the gpiolib irqchip helpers and now
     also suppors level-triggered interrupts.

   - 74x164 and RCAR now supports the .set_multiple() callback

   - AMDPT was converted to use generic GPIO.

   - TC3589x, TPS65218, SX150X, F7188X, MENZ127, VX855, WM831X, WM8994
     support the new single ended callback for open drain and in some
     cases open source.

   - Implement the .get_direction() callback for a few more drivers like
     PL061, Xgene.

  Cleanups:

   - Paul Gortmaker combed through the drivers and de-modularized those
     who are not really modules.

   - Move the GPIO poweroff DT bindings to the power subdir where they
     belong.

   - Rename gpio-generic.c to gpio-mmio.c, which is much more to the
     point.  That's what it is handling, nothing more, nothing less"

* tag 'gpio-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (126 commits)
  MIPS: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB
  gpio: zevio: make it explicitly non-modular
  gpio: timberdale: make it explicitly non-modular
  gpio: stmpe: make it explicitly non-modular
  gpio: sodaville: make it explicitly non-modular
  pinctrl: sh-pfc: Let gpio_chip.to_irq() return zero on error
  gpio: dwapb: Add ACPI device ID for DWAPB GPIO controller on X-Gene platforms
  gpio: dt-bindings: add wd,mbl-gpio bindings
  gpio: of: make it possible to name GPIO lines
  gpio: make gpiod_to_irq() return negative for NO_IRQ
  gpio: xgene: implement .get_direction()
  gpio: xgene: Enable ACPI support for X-Gene GFC GPIO driver
  gpio: tegra: Implement gpio_get_direction callback
  gpio: set up initial state from .get_direction()
  gpio: rename gpio-generic.c into gpio-mmio.c
  gpio: generic: fix GPIO_GENERIC_PLATFORM is set to module case
  gpio: dwapb: add gpio-signaled acpi event support
  gpio: dwapb: convert device node to fwnode
  gpio: dwapb: remove name from dwapb_port_property
  gpio/qoriq: select IRQ_DOMAIN
  ...
2016-05-17 17:39:42 -07:00
Linus Torvalds
16bf834805 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree updates from Jiri Kosina.

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (21 commits)
  gitignore: fix wording
  mfd: ab8500-debugfs: fix "between" in printk
  memstick: trivial fix of spelling mistake on management
  cpupowerutils: bench: fix "average"
  treewide: Fix typos in printk
  IB/mlx4: printk fix
  pinctrl: sirf/atlas7: fix printk spelling
  serial: mctrl_gpio: Grammar s/lines GPIOs/line GPIOs/, /sets/set/
  w1: comment spelling s/minmum/minimum/
  Blackfin: comment spelling s/divsor/divisor/
  metag: Fix misspellings in comments.
  ia64: Fix misspellings in comments.
  hexagon: Fix misspellings in comments.
  tools/perf: Fix misspellings in comments.
  cris: Fix misspellings in comments.
  c6x: Fix misspellings in comments.
  blackfin: Fix misspelling of 'register' in comment.
  avr32: Fix misspelling of 'definitions' in comment.
  treewide: Fix typos in printk
  Doc: treewide : Fix typos in DocBook/filesystem.xml
  ...
2016-05-17 17:05:30 -07:00
Linus Walleij
0d5358330c Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
This reverts commit 1d18a3f0f0.
2016-05-13 02:45:04 +02:00
Alexander Müller
d6d5c12535 pinctrl: meson: Fix eth_tx_en bit index
Fix pinctrl eth_tx_en bit index according to Hardkernel ODROID-C1 datasheet.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 14:18:10 +02:00
Geert Uytterhoeven
9697643ff3 pinctrl: sh-pfc: Let gpio_chip.to_irq() return zero on error
Currrently the gpio_chip.to_irq() callback returns -ENOSYS on error,
which causes bad interactions with the serial_mctrl_gpio helpers.

mctrl_gpio_init() returns -ENOSYS if GPIOLIB is not enabled, which is
intended to be ignored by its callers. However, ignoring -ENOSYS when it
was caused by a gpiod_to_irq() failure will lead to a crash later:

    Unable to handle kernel paging request at virtual address ffffffde
    ...
    PC is at mctrl_gpio_set+0x14/0x78

Fix this by returning zero instead, like gpiochip_to_irq() does.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 13:28:48 +02:00
Laxman Dewangan
1d18a3f0f0 pinctrl: tegra: avoid parked_reg and parked_bank
NVIDIA's Tegra210 support the park bit to make pinmux configuration
enable/disable. If parked bit is 1 then configuration does not apply
and if it is 0 then pinmux configuration applies. This is to support
to avoid any glitch in pinmux configurations.

The parked bit is part of mux register and mux bank and hence it is
not required to have member for the parked_reg and parked bank very
similar to other bit field of the same register.

Remove the need of the parked register and parked bank and get whether
parked function supported or not by parked_bit.

This is to make the parked bit handling same as other fields of mux
registers.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 13:26:30 +02:00
Laxman Dewangan
b22ef2a097 pinctrl: tegra: Correctly check the supported configuration
The pincontrol registers of Tegra chips has multiple filed per
registers. There is two type of registers mux and drive. All
configurations belongs to one of these registers.

If any configurations are supported then <config>_bit is set to
bit position of these registers otherwise -1 to not support it.
The member is defined as
	s32 <config>_bit:6;

So if config is not supported ifor given SoC then it is set to -1
in soc pinmmux table.
In common driver code, to find out that given config is supported
or not, it is checked as:

s8 bit = <config>_bit;
if (bit > 31) {
	/* Not supported config */
}

But in this case, bit is s8 and hence for non supporting it is -1.

Correct the check as:
if (bit < 0) {
	/* Not supported config */
}

Fixes: e4c02dced9 ("pinctrl: tegra: use signed bitfields for optional fields")
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 11:22:57 +02:00
Carlo Caione
468c234f9e pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
This patch adds the basic platform file to support the pin controller
found on the Amlogic Meson GXBB SoCs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 10:47:11 +02:00
David Wu
3ba6767a56 pinctrl: rockchip: fix pull setting error for rk3399
This patch fixes the pinctrl pull bias setting, since the pull up/down
setting is the contrary for gpio0(just the gpio0a and gpio0b) and
gpio2(just the gpio2c and gpio2d).

From the TRM said, the gpio0a pull polarity setting:
gpio0a_p
GPIO0A PE/PS programmation section, every
GPIO bit corresponding to 2bits[PS:PE]
2'b00: Z(Normal operation);
2'b11: weak 1(pull-up);
2'b01: weak 0(pull-down);
2'b10: Z(Normal operation);

Then, the other gpios setting as the following:
gpio1a_p (e.g.: gpio1, gpio2a, gpio2b, gpio3...)
GPIO1A PU/PD programmation section, every
GPIO bit corresponding to 2bits
2'b00: Z(Normal operation);
2'b01: weak 1(pull-up);
2'b10: weak 0(pull-down);
2'b11: Z(Normal operation);

For example,(rk3399evb board)
sdmmc_cd --->gpio0_a7
localhost / # io -r -4 0xff320040
ff320040: 00004d5f
In general,the value should be 0x0000cd5f since the pin has been set
in the dts.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: linux-gpio@vger.kernel.org
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11 10:43:21 +02:00
Patrice Chotard
3beed93c16 pinctrl: stm32: Implement .pin_config_dbg_show()
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-10 13:48:26 +02:00
Arnd Bergmann
4ace926172 phy: tegra: Changes for v4.7-rc1
This set of patches adds support for the Tegra XUSB pad controller. The
 controller provides a set of pads (lanes) that are used for I/O by other
 IP blocks within Tegra SoCs (PCIe, SATA and XUSB).
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Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Merge "phy: tegra: Changes for v4.7-rc1" from Thierry Reding:

This set of patches adds support for the Tegra XUSB pad controller. The
controller provides a set of pads (lanes) that are used for I/O by other
IP blocks within Tegra SoCs (PCIe, SATA and XUSB).

* tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  phy: tegra: Add Tegra210 support
  phy: Add Tegra XUSB pad controller support
  dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
  dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding
  phy: core: Allow children node to be overridden
  clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
2016-05-09 16:18:37 +02:00