Martin Blumenstingl 097145777c dt-bindings: reset: meson8b: fix duplicate reset IDs ... commit 4881873f4c upstream. According to the public S805 datasheet the RESET2 register uses the following bits for the PIC_DC, PSC and NAND reset lines: - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) Update the reset IDs of these three reset lines so they don't conflict with PIC_DC and map to the actual hardware reset lines. Fixes: 79795e20a1 ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-01-23 08:21:26 +01:00
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clock	clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328	2019-12-13 08:51:27 +01:00
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power	soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy	2019-12-13 08:52:17 +01:00
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regulator	…
reset	dt-bindings: reset: meson8b: fix duplicate reset IDs	2020-01-23 08:21:26 +01:00
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